MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 67

• Manufacturer Part Number: MCF5272VM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

The UART can be programmed to interrupt or wake up the CPU on various normal or abnormal events.
To reduce power consumption, the UART can be disabled by software if not in use.
1.2.4
The timer module contains five timers arranged in two submodules. One submodule contains a
programmable software watchdog timer. The other contains four independent, identical general-purpose
timer units, each containing a free-running 16-bit timer for use in various modes, including capturing the
timer value with an external event, counting external events, or triggering an external signal or interrupting
the CPU when the timer reaches a set value. Each unit has an 8-bit prescaler for deriving the clock input
frequency from the system clock or external clock input. The output pin associated with each timer has
programmable modes.
To reduce power consumption, the timer module can be disabled by software.
1.2.5
For system diagnostics and manufacturing testing, the MCF5272 includes user-accessible test logic that
complies with the IEEE 1149.1 standard for boundary scan testing, often referred to as JTAG (Joint Test
Action Group). The IEEE 1149.1 Standard provides more information.
1.3
This section presents issues to consider when designing with the MCF5272. It describes differences
between the MCF5272 (core and peripherals) and various other standard components that are replaced by
moving to an integrated device like the MCF5272.
1.3.1
The MCF5272 has flexibility in its system bus interfacing due to the dynamic bus sizing feature in which
32-,16-, and 8-bit data bus sizes are programmable on a per-chip select basis. The programmable nature of
the strobe signals (including OE/RD, R/W, BS[3:0], and CSn) should ensure that external decode logic is
minimal or nonexistent. Configuration software is required upon power-on reset before chip-selected
devices can be used, except for chip select 0 (CS0), which is active after power-on reset until programmed
otherwise. BUSW1 and BUSW0 select the initial data bus width for CS0 only. A wake-up from sleep mode
or a restart from stop mode does not require reconfiguration of the chip select registers or other system
configuration registers.
1.4
This section describes features peculiar to the MCF5272.
1.4.1
The physical layer interface controller (PLIC) allows the MCF5272 to connect at a physical level with
external CODECs and other peripheral devices that use either the general circuit interface (GCI), or
Freescale Semiconductor
MCF5272-Specific Features
System Design
Timer Module
Test Access Port
System Bus Configuration
Physical Layer Interface Controller (PLIC)
MCF5272 ColdFire
®
Integrated Microprocessor User’s Manual, Rev. 3
Overview
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