MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 351

• Manufacturer Part Number: MCF5272VM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

14.5.4
Figure 14-8
Table 14-6
The command and data RAM in the QSPI is indirectly accessible with QDR and QAR as 48 separate
locations that comprise 16 words of transmit data, 16 words of receive data and 16 bytes of commands.
A write to QDR causes data to be written to the RAM entry specified by QAR[ADDR]. This also causes
the value in QAR to increment.
Freescale Semiconductor
BIts
7–4
15
14
13
12
11
10
Address
9
8
3
2
1
0
Reset
Field
R/W
describes QIR fields.
WCEFB
WCEFE
ABRTB
ABRTE
ABRTL
SPIFE
WCEF
QSPI Interrupt Register (QIR)
WCEFB ABRTB
Name
ABRT
shows the QSPI interrupt register.
SPIF
—
—
—
—
15
Write collision access error enable. A write collision occurs during a data transfer when the RAM entry
containing the command currently being executed is written to by the CPU with the QDR. When this bit
is asserted, the write access to QDR results in an access error.
Abort access error enable. An abort occurs when QDLYR[SPE] is cleared during a transfer. When set,
an attempt to clear QDLYR[SPE] during a transfer results in an access error.
Reserved, should be cleared.
Abort lock-out. When set, QDLYR[SPE] cannot be cleared by writing to the QDLYR. QDLYR[SPE] is only
cleared by the QSPI when a transfer completes.
Write collision interrupt enable. Interrupt enable for WCEF. Setting this bit enables the interrupt, and
clearing it disables the interrupt.
Abort interrupt enable. Interrupt enable for ABRT flag. Setting this bit enables the interrupt, and clearing
it disables the interrupt.
Reserved, should be cleared.
QSPI finished interrupt enable. Interrupt enable for SPIF. Setting this bit enables the interrupt, and
clearing it disables the interrupt.
Reserved, should be cleared.
Write collision error flag. Indicates that an attempt has been made to write to the RAM entry that is
currently being executed. Writing a 1 to this bit clears it and writing 0 has no effect.
Abort flag. Indicates that QDLYR[SPE] has been cleared by the user writing to the QDLYR rather than
by completion of the command queue by the QSPI. Writing a 1 to this bit clears it and writing 0 has no
effect.
Reserved, should be cleared.
QSPI finished flag. Asserted when the QSPI has completed all the commands in the queue. Set on
completion of the command pointed to by QWR[ENDQP], and on completion of the current command
after assertion of QWR[HALT]. In wraparound mode, this bit is set every time the command pointed to
by QWR[ENDQP] is completed. Writing a 1 to this bit clears it and writing 0 has no effect.
MCF5272 ColdFire
14
— ABRTL WCEFE ABRTE — SPIFE
13
Figure 14-8. QSPI Interrupt Register (QIR)
12
Table 14-6. QIR Field Descriptions
®
Integrated Microprocessor User’s Manual, Rev. 3
11
0000_0000_0000_0000
10
MBAR + 0x00AC
R/W
9
Description
8
Queued Serial Peripheral Interface (QSPI) Module
7
—
4
WCEF ABRT — SPIF
3
2
1
0
14-13