MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 208

• Manufacturer Part Number: MCF5272VM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

SDRAM Controller
9.10.2
Like the read operations, shown in
issue the address (T1) and another (T2) to determine whether the access is page hit or miss. In the
burst-write, page-miss example, shown in
miss (T2), the precharge old page (T3) and activate new page cycles (T5) are required. Cycle T6 is a wait
state for SDRAM activation command as it is in
9-18
A10_PRECHG
SDADR[13:0]
SDBA[1:0]
SDCLKE
SDCLK
BS[3:0]
D[31:0]
SDWE
SDCS
RAS0
CAS0
SDRAM Write Accesses
T0
Figure 9-11. SDRAM Burst Write, 32-Bit Port, Page Miss, Access = 7-1-1-1
CF2 Core
T1
Address
Issue
MCF5272 ColdFire
T2
Miss?
Page
Hit or
Figure 9-9
Precharge
Old Page
T3
®
Bank x
Integrated Microprocessor User’s Manual, Rev. 3
Figure
T4
and
Figure
9-11, after the SDRAM determines that this is a page
Figure
New Page
T5
Activate
Bank y
Row
Row
9-9.
9-10, the write operations require one cycle to
T6
T7
Write
Data
1
Col
T8
Write
Data
2
Col
Bank y
Freescale Semiconductor
T9
Write
Data
3
Col
T10
Write
Data
4
Col
T11