MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 377

• Manufacturer Part Number: MCF5272VM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

16.3.15 UART Fractional Precision Divider Control Registers (UFPDn)
The UFPDn registers allow greater accuracy when deriving a transmitter/receiver clock source from
CLKIN. The use of the UFPDn registers is optional; if the contents are left in the reset state, code written
for other ColdFire devices containing UART modules will not be affected by the addition of these
registers. The contents of these registers allow the frequency to be divided by a factor of up to 16. When
autobaud is used, these registers are updated automatically to reflect the clock rate being used. Host
software can write to these registers to make fine adjustments to the clock rate. See
“Calculating Baud
Table 16-12
16.3.16 UART Input Port Registers (UIPn)
The UIP registers,
Table 16-13
Freescale Semiconductor
Bits
Bits
7–4
3–0
7–1
0
Address
Address
Reset
Field
Reset
Name
Name
R/W
CTS
Field
R/W
FD
—
—
describes UFPDn fields.
describes UIPn fields.
Reserved, should be cleared.
CTS state.The CTS value is latched and reflects the state of the input pin when UIPn is read. Note: This bit
has the same function and value as UIPCRn[RTS].
0 The current state of the CTS input is logic 0.
1 The current state of the CTS input is logic 1.
Reserved, should be cleared.
Fractional divider. The value of these bits, from 0 to 15, determine the scale factor by which the clocking source
for the transmitter and/or receiver is scaled.
Figure 16-18. UART Fractional Precision Divider Control Registers (UFPDn)
7
7
Figure
Rates,” for an example of UFPDn programming.
MCF5272 ColdFire
16-19, show the current state of the CTS input.
Figure 16-19. UART Input Port Registers (UIPn)
—
Table 16-12. UFPDn Field Descriptions
Table 16-13. UIPn Field Descriptions
®
MBAR + 0x130 (UFPD0), 0x170 (UFPD1)
Integrated Microprocessor User’s Manual, Rev. 3
MBAR + 0x134 (UIP0), 0x174 (UIP1)
4
—
0000_0000
1111_1111
Read only
Description
Description
R/W
3
FD
Section 16.5.1.2,
1
UART Modules
CTS
0
0
16-17