MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 130

• Manufacturer Part Number: MCF5272VM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

Debug Support
5.4.5
The data breakpoint register (DBR),
mode. DBR bits are masked by setting corresponding DBMR bits, as defined in TDR.
Table 5-9
Table 5-10
The DBR supports both aligned and misaligned references.
processor address, access size, and location within the 32-bit data bus.
5-12
31–0
31–0
Bits
Bits
DRc[4–0]
Reset
Field
R/W DBR is accessible in supervisor mode as debug control register 0x0E, using the WDEBUG instruction and
Name
Name
Data
Mask
describes DBR fields.
describes DBMR fields.
Data Breakpoint/Mask Registers (DBR, DBMR)
through the BDM port using the
DBMR is accessible in supervisor mode as debug control register 0x0F,using the WDEBUG instruction and
via the BDM port using the
31
Data breakpoint value. Contains the value to be compared with the data value from the processor’s local bus
as a breakpoint trigger.
Data breakpoint mask. The 32-bit mask for the data breakpoint trigger. Clearing a DBR bit allows the
corresponding DBR bit to be compared to the appropriate bit of the processor’s local data bus. Setting a
DBMR bit causes that bit to be ignored.
MCF5272 ColdFire
Figure 5-8. Data Breakpoint/Mask Registers (DBR and DBMR)
Table 5-11. Access Size and Operand Data Location
A[1:0]
00
01
10
11
0x
1x
xx
Table 5-10. DBMR Field Descriptions
WDMREG
Table 5-9. DBR Field Descriptions
Figure
®
RDMREG
Integrated Microprocessor User’s Manual, Rev. 3
command.
5-8, specify data patterns used as part of the trigger into debug
Access Size
Data (DBR); Mask (DBMR)
0x0E (DBR), 0x0F (DBMR)
and
Longword
Word
Word
Byte
Byte
Byte
Byte
WDMREG
Uninitialized
Description
Description
commands.
Table 5-11
Operand Location
D[31:24]
D[23:16]
D[31:16]
D[15:8]
D[15:0]
D[31:0]
D[7:0]
shows relationships between
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