MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 349

• Manufacturer Part Number: MCF5272VM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

Figure 14-5
14.5.2
Figure 14-6
Table 14-4
Freescale Semiconductor
14–8
Bits
7–0
15
Address
Reset
Field
R/W
Name
QCD
SPE
DTL
gives QDLYR field descriptions.
SPE
QSPI Delay Register (QDLYR)
shows the timing of the four SPI modes.
shows the QSPI delay register.
15
SCK
SCK
SCK
SCK
QSPI enable. When set, the QSPI initiates transfers in master mode by executing commands in the
command RAM. Automatically cleared by the QSPI when a transfer completes.The user can also clear this
bit to abort transfer unless QIR[ABRTL] is set. The recommended method for aborting transfers is to set
QWR[HALT].
QSPILCK Delay. When the DSCK bit in the command RAM, is set this field determines the length of the
delay from assertion of the chip selects to valid QSPI_CLK transition.
after the serial transfer.
Delay after transfer.When the DT bit in the command RAM sets this field determines the length of delay
14
(CPOL = 1, CPHA = 1)
(CPOL = 0, CPHA = 1)
(CPOL = 1, CPHA = 0)
(CPOL = 0, CPHA = 0)
MCF5272 ColdFire
Figure 14-6. QSPI Delay Register (QDLYR)
Table 14-4. QDLYR Field Descriptions
QCD
Figure 14-5. SPI Modes Timing
®
Integrated Microprocessor User’s Manual, Rev. 3
0000_0100_0000_0100
MBAR + 0x00A4
R/W
8
Description
7
Queued Serial Peripheral Interface (QSPI) Module
DTL
0
14-11