MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 508

• Manufacturer Part Number: MCF5272VM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

Electrical Characteristics
Table 23-18
1
2
23-24
Name
P14
P20
P15a
P15b
P16a
P16b
P17a
P17b
P19a
P19b
P22
P23
P24
P25
P25
P26
P26
FSR occurs on average every 125 μs.
In IDL slave mode, DCL may be any frequency multiple of 8 KHz between 256 KHz and 4.096 MHz inclusive.
1
2
FSR0, FSR1 period
FSR0 or FSC0 valid before the falling edge of DCL0 (setup time)
DCL clock frequency
DCL pulse-width high
DCL pulse-width low
FSR1 or FSC1 valid before the falling edge of DCL1 (setup time)
DCL0 to FSR0 or FSC0 input Invalid (hold time)
DCL1 to FSR1 or FSC1 input Invalid (hold time)
Delay from rising edge of DCL0 to low-z and valid data on DOUT0
Delay from rising edge of DCL1 to low-z and valid data on DOUT1 and
DOUT3
Delay from rising edge of DCL0 to high-z on DOUT0
Delay from rising edge of DCL1 to high-z on DOUT1 and DOUT3
Delay from rising edge of DCL1 to DFSC2, DFSC3 Invalid (output hold)
Data valid on DIN0 before falling edge of DCL0 (setup time)
Data valid on DIN1, DIN3 before falling edge of DCL1 (setup time)
Data valid on DIN0 after falling edge of DCL0 (hold time)
Data valid on DIN1, DIN3 after falling edge of DCL1 (hold time)
lists timing for IDL slave mode.
MCF5272 ColdFire
Table 23-18. IDL Slave Mode Timing, PLIC Ports 0–3
Characteristic
®
Integrated Microprocessor User’s Manual, Rev. 3
Min
256
25
45
25
45
25
25
—
—
—
—
25
25
25
25
—
2
Typ
125
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4096
Max
Freescale Semiconductor
55
55
30
30
30
30
—
—
—
—
—
—
—
—
—
—
% of DCL period
% of DCL period
Unit
Khz
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
μs