MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 432

• Manufacturer Part Number: MCF5272VM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

Signal Descriptions
19.6.4
Assertion of the transfer acknowledge (TA/PB5) input terminates an external bus cycle. It is enabled on a
per chip select basis by programming the wait state field to 0x1F in the corresponding chip select option
register (CSORn[WS]). This pin requires a 4.7-K¾ pull-up resistor or external logic that drives inactive
high.
TA must always be returned high before it can be detected again. Asserting TA into the next bus cycle has
no effect and does not terminate the bus cycle.
19.6.5
HiZ is a test signal. When it is connected to GND during reset, all output pins are driven to high impedance.
A 4.7-K¾ pullup resistor should be connected to this signal if the Hi-Z function is not used. Hi-Z
configuration input is sampled on the rising edge of Reset Output (RSTO).
19.6.6
Bypass is a Freescale test mode signal. This signal should be left unconnected.
19.6.7
RAS0 is the SDRAM row address strobe output.
19.6.8
CAS0 is the SDRAM column address strobe output.
19.6.9
The SDRAM clock output (SDCLK) is the same frequency as the CPU clock.
19.6.10 SDRAM Write Enable (SDWE)
This output is the SDRAM write enable.
19.6.11 SDRAM Clock Enable (SDCLKE)
This output is the SDRAM clock enable.
19-22
Transfer Acknowledge (TA/PB5)
Hi-Z
Bypass
SDRAM Row Address Strobe (RAS0)
SDRAM Column Address Strobe (CAS0)
SDRAM Clock (SDCLK)
Even though EBI modes set to SDRAM require setting the wait state field
in the chip select option register to 31, a low signal should never be applied
to TA during such accesses. For SDRAM accesses the bus cycle is
terminated internally by circuitry in the SDRAM module.
MCF5272 ColdFire
®
Integrated Microprocessor User’s Manual, Rev. 3
NOTE:
Freescale Semiconductor