MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 151

• Manufacturer Part Number: MCF5272VM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

5.5.3.3.12
The operand (longword) data is written to the specified debug module register. All 32 bits of the register
are altered by the write. DSCLK must be inactive while the debug module register writes from the CPU
accesses are performed using the WDEBUG instruction.
Command Format:
Table 5-3
Command Sequence:
Operand Data:
Result Data:
5.6
The ColdFire Family provides support debugging real-time applications. For these types of embedded
systems, the processor must continue to operate during debug. The foundation of this area of debug support
is that while the processor cannot be halted to allow debugging, the system can generally tolerate small
intrusions into the real-time operation.
The debug module provides three types of breakpoints—PC with mask, operand address range, and data
with mask. These breakpoints can be configured into one- or two-level triggers with the exact trigger
response also programmable. The debug module programming model can be written from either the
external development system using the debug serial interface or from the processor’s supervisor
programming model using the WDEBUG instruction. Only CSR is readable using the external
development system.
Freescale Semiconductor
15
Real-Time Debug Support
shows the definition of the DRc write encoding.
0x2
Write Debug Module Register (
MCF5272 ColdFire
12
Longword data is written into the specified debug register. The data is supplied
most-significant word first.
Command complete status (0xFFFF) is returned when register write is complete.
WDMREG
???
11
Figure 5-39.
Figure 5-40.
®
0xC
Integrated Microprocessor User’s Manual, Rev. 3
"NOT READY"
"ILLEGAL"
MS DATA
WDMREG
XXX
WDMREG
8
D[31:16]
D[15:0]
WDMREG
BDM Command Format
Command Sequence
7
"NOT READY"
"NOT READY"
NEXT CMD
LS DATA
100
)
5
"CMD COMPLETE"
NEXT CMD
4
DRc
Debug Support
0
5-33