HFIXF1110CC.B3-998844 Cortina Systems Inc, HFIXF1110CC.B3-998844 Datasheet - Page 125

• Manufacturer Part Number: HFIXF1110CC.B3-998844
• Description: IC ETHERNET MAC 10PORT 552-CBGA
• Manufacturer: Cortina Systems Inc

Specifications of HFIXF1110CC.B3-998844

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-4.2
• Voltage - Supply: 1.8 V, 2.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1010

IXF1110 MAC
Datasheet
250210, Revision 11.0
13 April 2009
8.5.1
Table 60
Table 61
Table 62
Table 63
Cortina Systems
MAC Control Registers
Table 60
associated with each MAC port. The register address is ‘Port_index + 0x**’, where the port
index is set at any value from 0x000 through 0x500. All registers are 32 bits.
Station Address Low ($ Port_Index + 0x00)
Station Address High ($ Port_Index + 0x01)
FDFC Type ($ Port_Index + 0x03)
FC TX Timer Value ($ Port_Index + 0x07)
®
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
31:16
15:0
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
31:16
31:16
31:0
15:0
15:0
Bit
Bit
Bit
Bit
through
Station
Address Low
Reserved
Station
Address High
Reserved
FDFC Type
Reserved
FC TX Timer
Value
Name
Name
Name
Name
Table 76 on page 132
Source MAC address bits 31-0.
This address is inserted in the source address field
when transmitting Pause frames, and is also used to
compare against unicast Pause frames at the
receiving side.
Reserved
Source MAC address bits 47-32.
This address is inserted in the source address field
when transmitting Pause frames, and is also used to
compare against unicast Pause frames at the
receiving side.
Reserved
Contains the value of the type field transmitted in an
internally generated flow control (pause) frame.
Internally generated flow control frames are
generated via the external pause interface or when
the RX FIFO exceeds its high watermark.
Reserved
The pause length sent to the receiving station in 512
bit times
provide details on the control and status registers
Description
Description
Description
Description
Type
Type
Type
Type
R/W
R/W
R/W
R/W
R
R
R
1
1
1
1
8.5 Memory Map
0x00000000
Default
Default
Default
Default
0x005E
0x0000
0x0000
0x0000
0x8808
0x0000
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