HFIXF1110CC.B3-998844 Cortina Systems Inc, HFIXF1110CC.B3-998844 Datasheet - Page 97

• Manufacturer Part Number: HFIXF1110CC.B3-998844
• Description: IC ETHERNET MAC 10PORT 552-CBGA
• Manufacturer: Cortina Systems Inc

Specifications of HFIXF1110CC.B3-998844

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-4.2
• Voltage - Supply: 1.8 V, 2.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1010

IXF1110 MAC
Datasheet
250210, Revision 11.0
13 April 2009
Note:
6.4
Note:
6.4.1
6.4.1.1
Cortina Systems
Pause control frame generation is enabled by default in the
0x12), on page
registers needed to set the RX FIFO watermarks.
Users should ensure that flow control is enabled to prevent RX FIFO overflows. If an RX
FIFO overflow occurs, data is sent out on the SPI4-2 interface regardless of the
Errored Frame Drop Enable ($ 0x59F), on page 150
EOP abort code to inform the upstream device that this data is corrupted.
Reset and Initialization
When powering up the IXF1110 MAC, the hardware reset signal (SYS_RES_L) should be
held active Low for a minimum of 100 ns after all of the power rails have fully stabilized to
their nominal values and the input clocks have reached their nominal frequency
(TDCLK = 400 MHz, CLK125 = 125 MHz, and CLK50 = 50 MHz).
In systems where the SYS_RES_L pin is driven from a single board-wide reset signal, the
switch or network processor only comes out of reset at the same time as the IXF1110 MAC,
or possibly later. This means the TDCLK may not be applied to theIXF1110 MAC when the
SYS_RES_L pin is released. However, the system designer must ensure that the switch or
network processor does not output TDCLK until it is stable and has reached its nominal
operating frequency. Failure to apply a stable TDCLK to the IXF1110 MAC can result in the
IXF1110 MAC training on a non-stable clock thus causing DIP4 errors and data corruption.
This will require a re-training once the TDCLK is stable.
When the TDCLK is applied after the reset pin is released, a built-in feature in the
IXF1110 MAC reactivates the internal reset once TDCLK is applied. The IXF1110 MAC
extends this hardware reset internally to ensure synchronization of all internal blocks within
the system. The internal reset is extended for a minimum of 4.11 ms after all clocks are
stable.
The device is correctly initialized at this point and ready for use. Clocks start to appear at
the relevant device ports and the SPI4-2 interface begins to source a training pattern on the
receive side while waiting for a training pattern on the transmit side. The SPI4-2 interface
synchronizes with the connected switch or network processor per the SPI4-2 Specification.
The CPU accesses can begin to configure the device for any existing user preferences
desired.By default, all ports on the IXF1110 MAC are enabled after power-up. The device is
ready for use at this time if the default settings are to be used. Otherwise, access the
required registers via the CPU interface and configure the control registers to the required
settings.
SPI4-2 Initialization
RX SPI4-2
After reset or Power-up the RX SPI4-2 interface will start to source training patterns on the
data bus to the upstream SPI4-2 device. The IXF1110 MAC will continue to send the
training patterns until a valid calendar is sent on RSTAT[1:0] from the upstream device to
the IXF1110 MAC. At this point, synchronization with the upstream device is complete and
the IXF1110 MAC will start to send data once data is available and a credit has been
granted from the RSTAT[1:0] bus.
When synchronization is completed, bit 13 of the
page 164
training patterns on the RX SPI4-2 data bus.
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
is “1”. Before completion, bit 13 is “0”, indicating the IXF1110 MAC is sending out
127.
Global RX Block Register Overview, on page 144
SPI4-2 RX Calendar ($ 0x702), on
settings. The data is marked with an
FC Enable ($ Port_Index +
6.4 Reset and Initialization
documents the
RX FIFO
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