HFIXF1110CC.B3-998844 Cortina Systems Inc, HFIXF1110CC.B3-998844 Datasheet - Page 96

• Manufacturer Part Number: HFIXF1110CC.B3-998844
• Description: IC ETHERNET MAC 10PORT 552-CBGA
• Manufacturer: Cortina Systems Inc

Specifications of HFIXF1110CC.B3-998844

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-4.2
• Voltage - Supply: 1.8 V, 2.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1010

IXF1110 MAC
Datasheet
250210, Revision 11.0
13 April 2009
6.3.1.3.1
6.3.1.3.2
6.3.1.3.3
6.3.2
Cortina Systems
Enabling the TX FIFO Drain
The TX FIFO drain is enabled using the
following occurs when the TX FIFO drain is enabled for a given port:
Putting the TX FIFO in Drain Mode
Use the TX FIFO drain when the link is down. The following is a step-by-step sequence to
put a port(s) into the TX FIFO drain mode:
Exiting the TX FIFO Drain Mode
To exit the TX FIFO drain mode.
RX FIFO
The IXF1110 MAC RX FIFOs are provisioned so that each port has its own 17.0 KB memory
space. This is enough memory to ensure against an over-run on any port while transferring
normal Ethernet frame-size data.
The RX FIFOs are configured by default to automatically generate Pause control frames to
initiate the following:
®
1. The system detects that link is down for a given port using bits 21:20 of the RX Config
2. Set the appropriate bit to 1 for the given port in the TX FIFO Drain Register ($0x620)
3. Set the MAC Soft Reset Register bit to 1 for the port(s) that has entered the TX FIFO
4. De-assert the MAC Soft Reset Register. Redo the MAC configurations. If applicable,
5. The connected SPI4-2 NPU or ASIC can now dump data to the port(s) that has entered
6. Monitor the RX Config Word Register to reestablish link with the link partner. Exit the TX
1. Set the TX FIFO Drain Register bits back to 0. This exits the TX FIFO drain mode and
2. The IXF1110 MAC is ready to resume normal data transmission.
• The TX FIFO is held in reset
• The FIFO status for that port indicates SATISFIED
• All data sent to that port is discarded
• Halt the link partner when the RX FIFO High Watermark is reached
• Restart the link partner when the data stored in the RXFIFO falls below the Low
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
Word Register ($ Port_Index + 0x16). The SPI4-2 TX FIFO port status is SATISFIED
when the link is down.
once link is down. This incurs the following:
a. Enables the drain mode
b. Causes the TX FIFO for the selected port to enter a reset state
c. Causes the TX FIFO SPI4-2 FIFO status for that port to change to STARVING.
drain mode.
re-enable auto-negotiation for the selected port(s) by setting bit 5 of the Diverse Config
Register back to 1.
the drain mode. All data sent to the port(s) selected is discarded and not recorded in
any register in the IXF1110 MAC.
FIFO drain mode when the system software detects link establishment.
the TX FIFO status bus now indicates the actual TX FIFO status.
Watermark.
TX FIFO Drain ($0x620), on page
6.3 TX FIFO and RX FIFO Operation
160. The
Page 96