HFIXF1110CC.B3-998844 Cortina Systems Inc, HFIXF1110CC.B3-998844 Datasheet - Page 18

• Manufacturer Part Number: HFIXF1110CC.B3-998844
• Description: IC ETHERNET MAC 10PORT 552-CBGA
• Manufacturer: Cortina Systems Inc

Specifications of HFIXF1110CC.B3-998844

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-4.2
• Voltage - Supply: 1.8 V, 2.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1010

IXF1110 MAC
Datasheet
250210, Revision 11.0
13 April 2009
4.0
4.1
4.1.1
4.1.2
4.2
Cortina Systems
Ball Assignments and Signal Descriptions
Naming Conventions
Signal Name Conventions
Signal names begin with a Signal Mnemonic, and can also contain one or more of the
following designations: a differential pair designation, a serial designation, a port
designation and an Active Low designation. Signal naming conventions are as follows:
Differential Pair + Port Designation. The positive and negative components of differential
pairs tied to a specific port are designated by the Signal Mnemonic, immediately followed by
an underscore and either P (positive component) or N (negative component), and an
underscore followed by the port designation. For example, SerDes interface signals for port
0 are identified as TX_P_0 and TX_N_0.
Serial Designation. A set of signals that are not tied to any specific port are designated by
the Signal Mnemonic, followed by a bracketed serial designation. For example, the set of 11
CPU Address Bus signals is identified as UPX_ADD[10:0].
Port Designation. Individual signals that apply to a particular port are designated by the
Signal Mnemonic, immediately followed by an underscore and the Port Designation. For
example, Optical module I
I
Active Low Designation. A control input or indicator output that is active Low is designated
by a final suffix consisting of an underscore followed by an upper case “L”. For example, the
CPU cycle complete identifier is shown as UPX_RDY_L.
Register Address Conventions
Registers located in on-chip memory are accessed using a register address, which is
provided in Hex notation. A Register Address is indicated by the dollar sign ($), followed by
the memory location in Hex.
Interface Signal Groups
This section describes the IXF1110 MAC signals in groups according to the associated
interface or function.
Table 10, Unused Balls/Reserved, on page 29
®
2
C_DATA_1, etc.
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
Figure 4
2
C Serial Data signals would be identified as I
and
Table 1, SPI4-2 Interface Signal Descriptions
describe the IXF1110 MAC signals.
4.0 Ball Assignments and Signal
2
C_DATA_0,
through
Descriptions
Page 18