HFIXF1110CC.B3-998844 Cortina Systems Inc, HFIXF1110CC.B3-998844 Datasheet - Page 81

• Manufacturer Part Number: HFIXF1110CC.B3-998844
• Description: IC ETHERNET MAC 10PORT 552-CBGA
• Manufacturer: Cortina Systems Inc

Specifications of HFIXF1110CC.B3-998844

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-4.2
• Voltage - Supply: 1.8 V, 2.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1010

IXF1110 MAC
Datasheet
250210, Revision 11.0
13 April 2009
Figure 23
Table 24
5.5.5
Note:
Cortina Systems
The operation of the LED Interface in Mode 0 is based on a 36-bit counter loop. The data for
each LED is placed in turn on the serial data line and clocked out by the LED_CLK.
Figure 23
each bit.
Figure 23
the falling edge of the clock and is valid for almost the entire clock cycle. This ensures that
the data is valid during the rising edge of the LED_CLK, which is used to clock the data into
the M5450 device.The actual data shown in
of which are valid LED DATA. The 36-bit data chain is built up as follows:
Mode 0 Timing
Mode 0 Clock Cycle to Data Bit Relationship
When implemented on a board with the M5450 device, the LED DATA bit 1 appears on
output bit 3 of the M5450 and the LED DATA bit 2 appears on output bit 4, etc. This means
that output bits 1, 2, 3, 34, and 35 will never have valid data and should not be used.
Mode 1: Detailed Operation
Please refer to manufacturers’ 74LS/HC595 datasheet for information on device operation.
The operation of the LED Interface in Mode 1 is again based on a 36-bit counter loop. The
data for each LED is placed in turn on the serial data line and clocked out by the LED_CLK.
Figure 24 on page 82
stream of each bit.
data changes on the falling edge of the clock and is valid for almost the entire clock cycle.
This ensures that the data is valid during the rising edge of the LED_CLK, which is used to
clock the data into the Shift Register chain devices.
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
LED_CLK CYCLE
LED_LATCH
LED_DATA
LED_CLK
34:36
4:33
2:3
1
shows the basic timing relationship and relative positioning in the data stream of
shows the 36 clocks that are output on the LED_CLK pin. The data changes on
Figure 24
1
START BIT
PAD BITS
LED DATA 1-30
PAD BITS
shows the basic timing relationship and relative positioning in the data
LED_DATA NAME
2
3
shows the 36 clocks that are output on the LED_CLK pin. The
1
4
23 24 25 26 27 28 29 30
26
This bit is used to synchronize the M5450 device to expect
35 bits of data to follow.
These bits are used only as fillers in the data stream to
extend the length from the actual 30 bit LED DATA to the
required 36-bit frame length. These bits should always be
a Logic 0.
These bits are the actual data transmitted to the M5450
device. The decode for each individual bit in each mode is
defined in
The data is TRUE. Logic 1(LED ON) = High
These bits are used as fillers in the data stream to extend
the length from the actual 30-bit LED DATA to the required
36-bit frame length. These bits should always be a Logic 0.
27
Figure 23
28
LED Signal Descriptions, on page
29
LED_DATA DESCRIPTION
consists of a chain of 36 bits only, 30
30
31
32
33
34
35
5.5 LED Interface
80.
36
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