HFIXF1110CC.B3-998844 Cortina Systems Inc, HFIXF1110CC.B3-998844 Datasheet - Page 126

• Manufacturer Part Number: HFIXF1110CC.B3-998844
• Description: IC ETHERNET MAC 10PORT 552-CBGA
• Manufacturer: Cortina Systems Inc

Specifications of HFIXF1110CC.B3-998844

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-4.2
• Voltage - Supply: 1.8 V, 2.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1010

IXF1110 MAC
Datasheet
250210, Revision 11.0
13 April 2009
Table 64
Table 65
Table 66
Cortina Systems
FDFC Address Low ($ Port_Index + 0x08)
FDFC Address High ($ Port_Index + 0x09)
IPG Transmit Time ($ Port_Index + 0x0C)
®
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
31:16
31:10
31:0
15:0
Bit
Bit
Bit
9:0
FDFC Address
Low
Reserved
FDFC Address
High
Reserved
IPG Transmit
Time
Name
Name
Name
Contains the value of the lowest 32 bits of the
destination address field transmitted in an internally
generated flow control (pause) frame. Internally
generated flow control frames are generated via the
external pause interface or when the RX FIFO
exceeds it high watermark.
Reserved
Contains the value of the highest 16 bits of the
destination address filed transmitted in an internally
generated flow control (pause) frame. Internally
generated flow control frames are generated via the
external pause interface or when the RX FIFO
exceeds it high watermark.
Reserved
IPG time for back-to-back transmissions (specified in
multiples of 8 bit times).
The value specified in this register is calculated as
follows: (register value + 4) *8 = IPG length in terms
of bit times. Therefore, the default value of 8 gives:
(8+4) *8 = 96 bit times.
96 bit times is the minimum IPG. If a value of 8 or
less is written to this register, the IPG remains 96 bit
times.
Description
Description
Description
Type
Type
Type
R/W
R/W
R/W
R
R
1
1
1
8.5 Memory Map
0xC2000001
Default
Default
Default
0x0000
0x0180
0x0000
0x0008
Page 126