HFIXF1110CC.B3-998844 Cortina Systems Inc, HFIXF1110CC.B3-998844 Datasheet - Page 68

• Manufacturer Part Number: HFIXF1110CC.B3-998844
• Description: IC ETHERNET MAC 10PORT 552-CBGA
• Manufacturer: Cortina Systems Inc

Specifications of HFIXF1110CC.B3-998844

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-4.2
• Voltage - Supply: 1.8 V, 2.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1010

IXF1110 MAC
Datasheet
250210, Revision 11.0
13 April 2009
5.3.3.1
Figure 16
5.3.3.2
Cortina Systems
Transmitter Operational Overview
The transmit section of the IXF1110 MAC has to serialize the Ten Bit Interface (TBI) data
from the IXF1110 MAC section and outputs this data at 1.25 GHz differential signal levels.
The 1.25 GHz differential SerDes signals are compliant with the Small Form Factor
Pluggable (SFP) Multi-Source Agreement (MSA).
The transmitter section takes the contents of the data register within the MAC and
synchronously transfers the data out, ten bits at a time – Least Significant Bit (LSB) first,
followed by the next Most Significant Bit (MSB). When these ten bits have been serialized
and transmitted, the next word of 10-bit data from the MAC is ready to be serialized for
transmission.
The data is transmitted by the high-speed current mode differential SerDes output stage
using an internal 1.25 GHz clock generated from the 125 MHz clock input.
Transmitter Concept
Transmitter Programmable Driver-Power Levels
The IXF1110 MAC SerDes core has programmable transmitter power levels to enhance
usability in any given application.The SerDes Registers are programmable to allow
adjustment of the transmit core driver output power. When driving a 100 Ω differential
terminated network, these output power settings effectively establish the differential voltage
swings at the driver output.
The (Register) allows the selection of 4 discrete power settings. The selected power setting
of these inputs is applied to each of the transmit cores drivers on a per-port basis.
SPI4-2 Interface Signal Summary, on page 54
transmit drivers as a function of the Driver Power Control inputs. The normalized current
®
TD0:TD9
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
LBENABLEx
Mux
DLCKx
8-/10-Bit
Register
TXDATAx
TXBYPASS
Select
Latch
Latch
lists the Normalized power setting of the
Mux
random code
generator
Pseudo-
Counter
Latch
shared across
the four links
Note: PLL is
recognition
PLL
Pattern
logic
Equalizer
Driver/
5.3 SerDes Interface
TXxDP/TXxON
LBERROR
B3377-01
Table 17,
x
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