HFIXF1110CC.B3-998844 Cortina Systems Inc, HFIXF1110CC.B3-998844 Datasheet - Page 5

• Manufacturer Part Number: HFIXF1110CC.B3-998844
• Description: IC ETHERNET MAC 10PORT 552-CBGA
• Manufacturer: Cortina Systems Inc

Specifications of HFIXF1110CC.B3-998844

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-4.2
• Voltage - Supply: 1.8 V, 2.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1010

IXF1110 MAC
Datasheet
250210, Revision 11.0
13 April 2009
6.0
7.0
8.0
Cortina Systems
5.8
Applications ................................................................................................................................. 92
6.1
6.2
6.3
6.4
6.5
6.6
6.7
Electrical Specifications ........................................................................................................... 102
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
Register Definitions................................................................................................................... 116
8.1
8.2
8.3
8.4
5.7.5
5.7.6
Clocks ................................................................................................................................. 90
5.8.1
5.8.2
5.8.3
5.8.4
5.8.5
Power Supply Sequencing.................................................................................................. 92
6.1.1
6.1.2
Analog Power Filtering........................................................................................................ 93
TX FIFO and RX FIFO Operation ....................................................................................... 93
6.3.1
6.3.2
Reset and Initialization........................................................................................................ 97
6.4.1
SerDes Power-Down Capabilities....................................................................................... 98
6.5.1
6.5.2
IXF1110 MAC Unused Ports .............................................................................................. 99
Optical Module Connections to the IXF1110 MAC ............................................................. 99
6.7.1
DC Specifications ............................................................................................................. 104
Undershoot/Overshoot Specifications .............................................................................. 105
CPU Timing Specification ................................................................................................. 106
JTAG Timing Specification ............................................................................................... 107
Transmit Pause Control Timing Specifications ................................................................. 108
Optical Module Interrupt and I
System Timing Specifications........................................................................................... 111
LED Timing Specifications................................................................................................ 111
SerDes Timing Specification............................................................................................. 112
SPI4-2 Timing Specifications............................................................................................ 114
Introduction ....................................................................................................................... 116
Document Structure.......................................................................................................... 116
Graphical Representation ................................................................................................. 116
Per Port Registers ............................................................................................................ 117
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
Boundary Scan Register........................................................................................ 89
Bypass Register..................................................................................................... 89
System Interface Reference Clocks ...................................................................... 90
5.8.1.1
5.8.1.2
SPI4-2 Receive and Transmit Data Path Clocks ................................................... 90
JTAG Clock............................................................................................................ 91
I
LED Clock.............................................................................................................. 91
Power-Up Sequence.............................................................................................. 92
Power-Down Sequence ......................................................................................... 92
TX FIFO ................................................................................................................. 94
6.3.1.1
6.3.1.2
6.3.1.3
RX FIFO................................................................................................................. 96
SPI4-2 Initialization ................................................................................................ 97
6.4.1.1
6.4.1.2
6.4.1.3
6.4.1.4
Placing the SerDes Port in Power-Down Mode ..................................................... 98
Bringing the SerDes Port Out of Power-Down Mode............................................. 98
SFP-to-IXF1110 MAC Connection......................................................................... 99
2
C Clock................................................................................................................ 91
CLK125 .................................................................................................. 90
CLK50 .................................................................................................... 90
MAC Transfer Threshold........................................................................ 94
TX FIFO Relation to the SPI4-2 Transmit FIFO Status (TSTAT)........... 95
TX FIFO Drain........................................................................................ 95
RX SPI4-2 .............................................................................................. 97
TX SPI4-2 .............................................................................................. 98
SerDes ................................................................................................... 98
CPU ....................................................................................................... 98
2
C Timing Specification ..................................................... 109
Contents
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