HFIXF1110CC.B3-998844 Cortina Systems Inc, HFIXF1110CC.B3-998844 Datasheet - Page 61

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HFIXF1110CC.B3-998844

Manufacturer Part Number
HFIXF1110CC.B3-998844
Description
IC ETHERNET MAC 10PORT 552-CBGA
Manufacturer
Cortina Systems Inc

Specifications of HFIXF1110CC.B3-998844

Controller Type
Ethernet Controller, MAC
Interface
SPI-4.2
Voltage - Supply
1.8 V, 2.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
575-BCBGA Exposed Pad (552 Bumps)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Other names
1008-1010

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IXF1110 MAC
Datasheet
250210, Revision 11.0
13 April 2009
5.2.2.2
5.2.2.3
5.2.2.4
5.2.2.5
5.2.2.6
5.2.2.7
5.2.2.8
Cortina Systems
CALENDAR_M
CALENDAR_M specifies the number of times the calendar port status sequence is
repeated between the framing and DIP2 cycle of the calendar sequence.
In the IXF1110 MAC, the TX path CALENDAR_M is fixed at 1; thus, the port status for ports
0 - 9 will be transmitted only once between the framing and DIP2 cycle of the calendar
sequence.
In the IXF1110 MAC, the RX path CALENDAR_M is also fixed at 1. Thus, the status for port
0-9 must only be sent once between framing and DIP2.
Therefore, the value of both Tx and RX CALENDAR_M parameters is always fixed a 1.
DIP2_Thr
DIP2_Thr is a parameter specifying the number of consecutive correct DIP2s required by
the RX SPI4-2 to validate a calendar sequence and therefore terminate sending training
sequences. In
parameter. The default value for DIP2_Thr is 1.
Loss_Of_Sync
Loss_of_Sync is a parameter specifying the number of consecutive framing calendar cycles
required to indicate a loss of synchronization and therefore restart training sequences. In
SPI4-2 RX Calendar ($ 0x702), on page
value for Loss_Of_Sync is three.
DATA_MAX_T
DATA_MAX_T is an RX SPI4-2 parameter specifying the interval between transmission of
periodic training sequences. In
specify this parameter. The default value for DATA_MAX_T is 0x0000, which disables
periodic training sequence transmission.
REP_T
REP_T is an RX SPI4-2 parameter specifying the number of repetitions of the training
sequence to be scheduled every DATA_MAX_T interval. In
on page
DIP4_UnLock
DIP4_UnLock is a TX SPI4-2 parameter specifying the number of consecutive incorrect
DIP4 fields to be detected in order to declare loss of synchronization and drive TSTAT[1:0]
bus with framing. In
this parameter. The default value for DIP4_UnLock is 0x4.
DIP4_Lock
DIP4_Lock is a TX SPI4-2 parameter specifying the number of consecutive correct DIP4
fields to be detected in order to declare synchronization achieved and enable the calendar
sequence. In
parameter. The default value for DIP4_Lock is 0x20.
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
163, bits 23 to 16 specify this parameter. The default value for REP_T is 0x00.
SPI4-2 TX Synchronization ($ 0x703), on page
SPI4-2 RX Calendar ($ 0x702), on page
SPI4-2 TX Synchronization ($ 0x703), on page
SPI4-2 RX Training ($ 0x701), on page
164, bits 11 to 8 specify this parameter. The default
164, bits 19 to 16 specify this
5.2 System Packet Interface Level 4
SPI4-2 RX Training ($ 0x701),
165, bits 7 to 0 specify this
165, bits 15 to 8 specify
163, bits 15 to 0
Page 61
Phase 2

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