HFIXF1110CC.B3-998844 Cortina Systems Inc, HFIXF1110CC.B3-998844 Datasheet - Page 69

• Manufacturer Part Number: HFIXF1110CC.B3-998844
• Description: IC ETHERNET MAC 10PORT 552-CBGA
• Manufacturer: Cortina Systems Inc

Specifications of HFIXF1110CC.B3-998844

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-4.2
• Voltage - Supply: 1.8 V, 2.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1010

IXF1110 MAC
Datasheet
250210, Revision 11.0
13 April 2009
Table 21
5.3.3.3
Figure 17
Cortina Systems
setting is 10 mA which corresponds to the normalized power setting of 1.0. This is the
default setting of the IXF1110 MAC SerDes interface. Other values listed in the Normalized
Driver Power Setting column are multiples of 10 mA. For example, with inputs at 1110, the
driver power is 0.5 x 10 mA = 5 mA.
SerDes Driver TX Power Levels
Receiver Operational Overview
The receiver structure performs Clock and Data Recovery (CDR) on the incoming serial
data stream. The quality of this operation is a dominant factor for the Bit Error Rate (BER)
system performance. Feed forward and feedback controls are combined in one receiver
architecture for enhanced performance. The data is over-sampled and a digital circuit
detects the edge position in the data stream. A signal is not generated if an edge is not
found. A feedback loop takes care of low-frequency jitter phenomenon of unlimited
amplitude, while a feed forward section suppresses high-frequency jitter having limited
amplitude. The static edge position is held at a constant position in the over-sampled by a
constant adjustment of the sampling phases with the early and late signals.
Receiver Concept
®
Note:
DRVPWRx[3]
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
RXxIP/RXxIN
0
1
1
1
All other values are reserved.
LEWRAPx
DRVPWRx[2
Note: PLL is
across the
four links
0
0
1
1
]
shared
Mux
PLL
Sample
latches
RG
DRVPWRx[1]
TXxDP/TXxON
Digital edge detection
Digital data detection
Early/late gate
1
1
0
1
AND
Selector
Counter
DRVPWRx[0]
1
1
1
0
Register
Shift
Driver Power
Normalized
random code
generator
Setting
Pseudo-
8-/10-Bit
Register
1.33
2.0
1.0
0.5
RXDATAx
DLCKx
DATASYNC
recognition
Pattern
5.3 SerDes Interface
logic
RD0:RD9
Driver Power
13.3 mA
20 mA
10 mA
5 mA
LBERRORx
B3378-01
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