HFIXF1110CC.B3-998844 Cortina Systems Inc, HFIXF1110CC.B3-998844 Datasheet - Page 164

• Manufacturer Part Number: HFIXF1110CC.B3-998844
• Description: IC ETHERNET MAC 10PORT 552-CBGA
• Manufacturer: Cortina Systems Inc

Specifications of HFIXF1110CC.B3-998844

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-4.2
• Voltage - Supply: 1.8 V, 2.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1010

IXF1110 MAC
Datasheet
250210, Revision 11.0
13 April 2009
Table 103
Cortina Systems
SPI4-2 RX Calendar ($ 0x702)
®
Register Description: SPI4-2 RX interface start-up parameters for FIFO status calendar
operation.
1. R = Read Only; CoR = Clear on Read; W = Write only; R/W = Read/Write
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
31:30
27:21
19:16
15:14
11:8
Bit
7:4
3:0
29
28
20
13
12
RSCLK_invert
TSCLK_invert
Reserved
DIP-2_Thr
Reserved
Reserved
Reserved
RX Train Test
Modes
DIP2_Error
RX SPI4-2 Sync
TX SPI4 Sync
Loss_of_Sync
Name
00 = Normal mode
01 = Do not enter training based on a
repeating “11” pattern on RSTAT[1:0]
1x = Train continuously
0 = The FIFO status is captured on the rising
1 = The FIFO status is captured on the falling
Note:
0 = The FIFO status is launched on the rising
1 = The FIFO status is launched on the
Reserved
Set based on an incorrect RX DIP2 result.
This bit is cleared upon a read
Defines how many consecutive correct
DIP-2s are required to disable sending of
training sequences on the RX SPI4-2.
Reserved
0 = RX SPI4 In Training (RDAT = training)
1 = RX SPI4 Out Of Training (RDAT = idles)
0 = TX SPI4-2 Calendar is in constant
1 = The TX SPI4-2 has received the valid
Loss-of-Sync is a parameter specifying the
number of consecutive framing calendar
cycles required to indicate a loss of
synchronization and restart training
sequences.
Reserved
Write as 0, ignore on Read.
edge of the RSCLK as per the SPI4-2
specification
edge of RSCLK
edge of the TSCLK as per the SPI4-2
specification
falling edge of TSCLK
Framing
training patterns on TDAT and is now
sending a 10 port Calendar on TSAT with
valid FIFO information
For proper operation, set this bit to
the desired setting before the
RSCLK is applied to the device.
Description
Type
CoR
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
1
8.5 Memory Map
0x00010300
Default
Value
0x000
0x0
0x0
0x1
0x3
0x0
0x0
00
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