HFIXF1110CC.B3-998844 Cortina Systems Inc, HFIXF1110CC.B3-998844 Datasheet - Page 73

• Manufacturer Part Number: HFIXF1110CC.B3-998844
• Description: IC ETHERNET MAC 10PORT 552-CBGA
• Manufacturer: Cortina Systems Inc

Specifications of HFIXF1110CC.B3-998844

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-4.2
• Voltage - Supply: 1.8 V, 2.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1010

IXF1110 MAC
Datasheet
250210, Revision 11.0
13 April 2009
5.4.3.2.7
Note:
Note:
5.4.4
5.4.4.1
Cortina Systems
RX_LOS_INT
RX_LOS_INT is a single output, open-drain type signal, and is active Low. A change in state
of any of the RX_LOS_0:9 inputs causes this signal to switch Low and remain in this state
until a Read of the Optical Module Status register has taken place. The signal then returns
to an inactive state.
The RX_LOS_0:9 inputs shown in
are synchronized with an internal system clock. This results in a delay from the time the
signal is active to the register bit and/or interrupt being set.
MOD_DEF_INT, TX_FAULT_INT, and RX_LOS_INT are open-drain type outputs. With the
three signals on the device, the system can decide which Optical module Status Register
bits to look at to identify the interrupt condition source port. However, this is achieved at the
expense of two device pins.
In systems that cannot support multiple interrupt signals (applications that do not have extra
hardware pins), these three outputs can be connected to a single pull-up resistor and used
as a single interrupt pin.
I2C Module Configuration Interface
The I
the SFP multi-source agreement (MSA). This document details the contents of the registers
and addresses accessible on a given optical module supporting this interface.
The SFP MSA identifies up to 512 8-bit registers that are accessible in each optical module.
The I
the 8-bit parameters. The maximum clock rate of the interface is 100 kHz. All address select
pins on the internal E
The specific interface in the IXF1110 MAC supports only a subset of the full I
and only the features required to support the optical modules are implemented, leading to
the following support features:
General Description
In the IXF1110 MAC, the entire I
Data Registers (see
($ 0x79C), on page
The I
®
• Single I
• Ten per-port I
• Due to the single internal controller, only one optical module may be accessed at any
• The I
• Port Address Error
• Write Protect Error bit
• No Acknowledge Error bit
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
pin use.
module requirement that all modules must be addressed as 00h.
one time. Optical module accesses contains a single register Read. Since these
register accesses will most likely be done during power-up or discovery of a new
module, these restrictions should not affect normal operation.
2
2
2
C interface is supported on SFP optical modules. Details of the operation are found in
C interface is Read/Write capable and supports either sequential or random access to
C Control Register is divided into the following sections:
2
C interface also supports byte write accesses to the full address range.
2
C_CLK pin connected to all modules, and implemented to save unnecessary
2
C_DATA pins optical (I
168. The general operation is described below.
I
2
2
C Control Ports 0-9 ($ 0x79B), on page 167
PROM are tied Low to give a device address equal to zero (00h).
2
C interface is controlled through separate I
Optical Module Status Ports 0-9 ($ 0x799), on page 166
2
C_DATA_9:0) are required due to the optical
5.4 Optical Module Interface
and
I
2
C Data Ports 0-9
2
2
C Control and
C interface,
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