HFIXF1110CC.B3-998844 Cortina Systems Inc, HFIXF1110CC.B3-998844 Datasheet - Page 162

• Manufacturer Part Number: HFIXF1110CC.B3-998844
• Description: IC ETHERNET MAC 10PORT 552-CBGA
• Manufacturer: Cortina Systems Inc

Specifications of HFIXF1110CC.B3-998844

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-4.2
• Voltage - Supply: 1.8 V, 2.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1010

IXF1110 MAC
Datasheet
250210, Revision 11.0
13 April 2009
Table 100
8.5.7
Table 101
Cortina Systems
TX FIFO Number of Frames Removed Ports 0-9 ($ 0x622 - 0x62B)
SPI4-2 Block Register Overview
Table 101
Registers.
SPI4-2 RX Burst Size ($ 0x700) (Sheet 1 of 2)
®
TX FIFO Number
of Frames
Removed on Port 0
TX FIFO Number
of Frames
Removed on Port 1
TX FIFO Number
of Frames
Removed on Port 2
TX FIFO Number
of Frames
Removed on Port 3
TX FIFO Number
of Frames
Removed on Port 4
TX FIFO Number
of Frames
Removed on Port 5
TX FIFO Number
of Frames
Removed on Port 6
TX FIFO Number
of Frames
Removed on Port 7
TX FIFO Number
of Frames
Removed on Port 8
TX FIFO Number
of Frames
Removed on Port 9
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
Register Description: SPI4-2 RX interface start-up parameters for burst size.
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
30:25
Bit
31
Name
through
idles
Reserved
Name
Description
This register counts the number of frames
removed on port 0 due to a TX FIFO overflow.
This register counts the number of frames
removed on port 1 due to a TX FIFO overflow.
This register counts the number of frames
removed on port 2 due to a TX FIFO overflow.
This register counts the number of frames
removed on port 3 due to a TX FIFO overflow.
This register counts the number of frames
removed on port 4 due to a TX FIFO overflow.
This register counts the number of frames
removed on port 5 due to a TX FIFO overflow.
This register counts the number of frames
removed on port 6 due to a TX FIFO overflow.
This register counts the number of frames
removed on port 7 due to a TX FIFO overflow.
This register counts the number of frames
removed on port 8 due to a TX FIFO overflow.
This register counts the number of frames
removed on port 9 due to a TX FIFO overflow.
Table 104 on page 165
0 = Zero idle insertion between transfer bursts
1 = Inserts four idle control words between
Reserved
each burst. (This occurs not only on an
EOP, but also at the end of every
MaxBurst1 or MaxBurst2.
Description
provide an overview of the SPI4-2 Block
Address
0x62A
0x62B
0x622
0x623
0x624
0x625
0x626
0x627
0x628
0x629
Type
R/W
Type
CoR
CoR
CoR
CoR
CoR
CoR
CoR
CoR
CoR
CoR
R
1
1
8.5 Memory Map
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00060002
Default
Default
0x00
0x0
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