HFIXF1110CC.B3-998844 Cortina Systems Inc, HFIXF1110CC.B3-998844 Datasheet - Page 75

• Manufacturer Part Number: HFIXF1110CC.B3-998844
• Description: IC ETHERNET MAC 10PORT 552-CBGA
• Manufacturer: Cortina Systems Inc

Specifications of HFIXF1110CC.B3-998844

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-4.2
• Voltage - Supply: 1.8 V, 2.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1010

IXF1110 MAC
Datasheet
250210, Revision 11.0
13 April 2009
5.4.4.1.2
Note:
Cortina Systems
Write Access Operation Example
The following sequence provides an example of writing data to the Optical Module Register
0xFF for Port 9:
All other bits in this register should be written with the value ‘0’.
This data is written into the I
Only one optical module I
Write is carried out to the I
Write, the data for the first Write is lost. To ensure no data is lost, make sure Write
complete = 1 before starting the next Write sequence.
®
3. The state machine uses the data in the Device ID and Register Address fields to build
4. The I
5. The I
6. The data is read through the CPU interface. The CPU must poll the Read Data Valid bit
1. Program the
2. When this register is written and the I
3. The state machine uses the data in the Device ID and Register Address fields to build
4. The I
5. The I
6. The data is written through the CPU interface. The CPU must poll the Write_Complete
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
the data frame to be sent to the optical module.
the actual data between the IXF1110 MAC and the selected optical module (refer to the
details in
Read_Data field, bits [7:0] of the I
bit 20 of the I
until it is set to ‘1. Only once this bit is set, it is safe to read the data in the I
Register.
information:
a. Enable I
b. Set the port to be accessed by setting bits [19:16] to 0x9.
c. Select a WRITE access by setting bit 15 to ‘0’.
d. Set the Device ID, bits [14:11] to be 0xA (Atmel compatible).
e. Set the 11-bit Register Address, bits [10:0] to 0xFF.
f.
machine examines the Port Address Select and enables the I
the selected port.
the data frame to be sent to the optical module.
the actual data between the IXF1110 MAC and the selected optical module (refer to the
details in
field, bits [23:16] of the I
the I
bit until it is set to ‘1. Only once this bit is set, it is safe to request a new access.
Initiate the I
2
2
2
2
2
C Control Register to ‘1’ to signify that the Write Access is complete.
C DATA_READ_FSM internal state machine takes over the task of transferring
C DATA_READ_FSM internal state machine places the received data into the
C DATA_WRITE_FSM internal state machine takes over the task of transferring
C DATA_WRITE_FSM internal state machine uses the data from the Write_Data
Section 5.4.4.2, I
Section 5.4.4.2, I
2
2
I
C Block by setting bit 25 to ‘1’.
2
C Control Register to ‘1’ to signify that the Read data is valid.
C Control Ports 0-9 ($ 0x79B), on page 167
2
C transfer by setting bit 24 to ‘1’.
2
2
C access sequence can be run at any given time. If a second
C Control Register before a result is returned for the previous
2
2
C Control Register in a single cycle via the CPU interface.
C Data Register, and sets the Write_Complete bit, bit 22 of
2
2
C Protocol Specifics, on page
C Protocol Specifics, on page
2
C Data Register, and sets the Read Data Valid bit,
2
C Start bit is at a Logic 1, the I
76).
76).
with the following
5.4 Optical Module Interface
2
C_DATA_0:9 output for
2
C access state
2
C Data
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