HFIXF1110CC.B3-998844 Cortina Systems Inc, HFIXF1110CC.B3-998844 Datasheet - Page 64

• Manufacturer Part Number: HFIXF1110CC.B3-998844
• Description: IC ETHERNET MAC 10PORT 552-CBGA
• Manufacturer: Cortina Systems Inc

Specifications of HFIXF1110CC.B3-998844

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-4.2
• Voltage - Supply: 1.8 V, 2.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1010

IXF1110 MAC
Datasheet
250210, Revision 11.0
13 April 2009
Figure 14
Cortina Systems
FIFO Status State Diagram
The FIFO status of each port is encoded in a 2-bit data structure, which is defined in
Status Format, on page
TSTAT[1]/RSTAT[1] and the least significant bit is sent over TSTAT[0]/RSTAT[0]. The “1 1”
pattern is reserved for In-band framing, which must be sent once prior to the start of the
FIFO status sequence.
Immediately before the “1 1” framing pattern, a DIP-2 odd parity checksum is sent at the
end of each complete sequence. The DIP-2 code is computed diagonally over
TSTAT[1]/RSTAT[1] and TSTAT[0]/RSTAT[0] for all preceding FIFO status indications sent
after the last “1 1” framing pattern, as shown in
page
parity bits are computed by summing diagonally. Bits a and b in line 9 correspond to the
space occupied by the DIP-2 parity bits and are set to 1 during encoding. The “1 1” framing
pattern is not included in the parity calculation. The procedure described applies to either
parity generation on the egress path or to check parity on the ingress path.
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
65. The first word is at the top of the figure and the last word is at the bottom. The
DIP-2
Disable
66. The most significant bit of each port status is sent over
SYNC 11
Disable
Enable
11
Port 0
Port 5
Figure 15, Example of DIP-2 Encoding, on
Port 1
Port 6
Port 2
Port 7
5.2 System Packet Interface Level 4
Port 3
Port 8
Port 4
Port 9
Page 64
Phase 2
FIFO