HFIXF1110CC.B3-998844 Cortina Systems Inc, HFIXF1110CC.B3-998844 Datasheet - Page 131

• Manufacturer Part Number: HFIXF1110CC.B3-998844
• Description: IC ETHERNET MAC 10PORT 552-CBGA
• Manufacturer: Cortina Systems Inc

Specifications of HFIXF1110CC.B3-998844

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-4.2
• Voltage - Supply: 1.8 V, 2.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1010

IXF1110 MAC
Datasheet
250210, Revision 11.0
13 April 2009
Table 74
Cortina Systems
RX Packet Filter Control ($ Port_Index + 0x19) (Sheet 1 of 2)
®
Register Description: This register allows for specific packet types to be marked for filtering,
and is used in conjunction with the RX FIFO Errored Frames Drop Enable Register
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
2. Jumbo frames (1519 - 9600 bytes), matching the filter conditions, which would cause the frame to be
3. Frames are dropped only when the appropriate bits are set in the RX FIFO Errored Frame Drop Enable
31:6
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
Bit
5
4
3
dropped by the RX FIFO, will not be dropped. Instead, jumbo frames that are marked to be dropped by the
RX FIFO, based on the filter setting in this register, will still be sent across the SPI4-2 interface, but will be
marked as an EOP abort frame. Thus, jumbo frames matching the filter conditions will not be counted in
the RX FIFO Number of Frames Removed Register because they are not removed by the RX FIFO. Only
standard packet sizes (64 - 1518 bytes) meeting the filter conditions set in this register will actually be
dropped by the RX FIFO and counted in the RX FIFO Number of Frames Removed.
Register (
frames are sent across the SPI4-2 interface and marked as EOP abort frames.
Reserved
CRC Error Pass
Pause Frame
Pass
VLAN Drop En
RX FIFO Errored Frame Drop Enable ($ 0x59F)
Name
2
2
Reserved
This bit enables a Global filter on frames with a CRC
Error.
When CRCErrorPASS = 0, all frames with a CRC
Error are marked as bad.
NOTE: When used in conjunction with the RX FIFO
ErroredFrameDropEnable[9:0] Register (see
Errored Frame Drop Enable ($ 0x59F)
the frame to be dropped in the RX FIFO. Otherwise,
the frame is sent across the SPI4-2 interface but
marked as an EOP Abort frame.
When the CRC Error Pass Filter bit = 0, it takes
precedence over the other filter bits. Any packet
regardless if it is a Pause, Unicast, Multicast or
Broadcast packet with a CRC error will be marked as
bad frames when CRC Error Pass = 0
When CRCErrorPASS = 1, frames with a CRC Error
are not marked as bad and are passed to the SPI4-2
interface for transfer as good frames, regardless of
the state of the FrameDropEn[9:0] bits.
This bit enables a Global filter on Pause frames.
When PauseFramePass = 0, all Pause frames are
marked as bad.
NOTE: When used in conjunction with the RX FIFO
ErroredFrameDropEnable[9:0] Register (see
Errored Frame Drop Enable ($ 0x59F)
the frame to be dropped in the RX FIFO. Otherwise,
the frame is sent across the SPI4-2 interface but
marked as an EOP Abort frame.
Note:
This bit enables a Global filter on VLAN frames.
When VLANDropEn = 0, all VLAN frames are passed
to the SPI4-2 Interface.
When VLANDropEn = 1, all VLAN frames are
dropped.
When PauseFramePass = 1, all Pause
frames are not marked as bad and are
passed to the SPI4-2 interface for transfer as
good frames, regardless of the state of the
FrameDropEn[9:0] bits.
3
Description
). When the appropriate bits are not set, the
). This allows
). This allows
RX FIFO
RX FIFO
Type
R/W
R/W
R/W
R
8.5 Memory Map
1
0x00000000
0x000000
Default
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0
0
0