HFIXF1110CC.B3-998844 Cortina Systems Inc, HFIXF1110CC.B3-998844 Datasheet - Page 7

• Manufacturer Part Number: HFIXF1110CC.B3-998844
• Description: IC ETHERNET MAC 10PORT 552-CBGA
• Manufacturer: Cortina Systems Inc

Specifications of HFIXF1110CC.B3-998844

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-4.2
• Voltage - Supply: 1.8 V, 2.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1010

IXF1110 MAC
Datasheet
250210, Revision 11.0
13 April 2009
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Cortina Systems
IXF1110 MAC Block Diagram........................................................................................................ 15
IXF1110 MAC System Block Diagram........................................................................................... 16
552-Ball CBGA Assignments (Top View) ...................................................................................... 17
Interface Diagram .......................................................................................................................... 19
Packet Buffering FIFO ................................................................................................................... 45
Ethernet Frame Format ................................................................................................................. 45
PAUSE Frame Format................................................................................................................... 46
Transmit Pause Control Interface.................................................................................................. 48
SPI4-2 Interfacing with the Network Processor or Forwarding Engine.......................................... 54
Data Path State ............................................................................................................................. 56
Per-Port State Diagram with Transitions at Control Words ........................................................... 58
DIP-4 Calculation Boundaries ....................................................................................................... 59
DIP-4 Calculation Algorithm .......................................................................................................... 60
FIFO Status State Diagram ........................................................................................................... 64
Example of DIP-2 Encoding ......................................................................................................... 65
Transmitter Concept ...................................................................................................................... 68
Receiver Concept .......................................................................................................................... 69
Data Validity Timing....................................................................................................................... 76
Start and Stop Definition Timing.................................................................................................... 77
Acknowledge Timing ..................................................................................................................... 77
Random Read ............................................................................................................................... 78
Byte Write ...................................................................................................................................... 79
Mode 0 Timing............................................................................................................................... 81
Mode 1 Timing............................................................................................................................... 82
CPU Interface Inputs/Outputs........................................................................................................ 85
Read Timing – Asynchronous Interface ........................................................................................ 87
Write Timing – Asynchronous Interface......................................................................................... 87
Power Sequencing ........................................................................................................................ 92
Analog Power Supply Filter Network ............................................................................................. 93
Packet Buffering FIFO ................................................................................................................... 94
SFP-to-IXF1110 MAC Connection ................................................................................................ 99
CPU Port Read Timing ................................................................................................................ 106
CPU Port Write Timing ................................................................................................................ 106
JTAG Timing................................................................................................................................ 107
Transmit Pause Control Interface................................................................................................ 108
Optical Module Interrupt Timing .................................................................................................. 109
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Hardware Reset Timing............................................................................................................... 111
LED Timing.................................................................................................................................. 111
SerDes Timing............................................................................................................................. 112
SPI4-2 Transmit FIFO Status Bus Timing ................................................................................... 114
SPI4-2 Receive FIFO Status Bus Timing .................................................................................... 114
Memory Overview........................................................................................................................ 117
Register Overview ....................................................................................................................... 118
RoHS Compliant CBGA Package Diagram (Side View).............................................................. 170
RoHS Compliant CBGA Package Diagram (Bottom and Top View) ........................................... 171
Non-RoHS Compliant CBGA Package Diagram (Side View)...................................................... 172
Non-RoHS Compliant CBGA Package Diagram (Bottom and Top View) ................................... 173
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C Bus Timing ............................................................................................................................ 109
C Write Cycle ............................................................................................................................ 110
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IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
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