HFIXF1110CC.B3-998844 Cortina Systems Inc, HFIXF1110CC.B3-998844 Datasheet - Page 87

• Manufacturer Part Number: HFIXF1110CC.B3-998844
• Description: IC ETHERNET MAC 10PORT 552-CBGA
• Manufacturer: Cortina Systems Inc

Specifications of HFIXF1110CC.B3-998844

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-4.2
• Voltage - Supply: 1.8 V, 2.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1010

IXF1110 MAC
Datasheet
250210, Revision 11.0
13 April 2009
.
Figure 26
5.6.2.2
Figure 27
Cortina Systems
Read Timing – Asynchronous Interface
Write Access
The IXF1110 MAC Write access cycle operation is done in the following order:
Figure 27
Write Timing – Asynchronous Interface
®
UPX_DATA[31:0]
1. Chip Select (UPX_CS_L) is asserted at all times for the duration of the operation. The
2. UPX_WR_L should be asserted by the CPU. The IXF1110 MAC latches the address.
3. The CPU drives valid data onto the processor bus (UPX_DATA[31:0]).
4. The CPU de-asserts the asynchronous Write signal (UPX_WR_L) of the IXF1110 MAC.
5. The IXF1110 MAC asserts asynchronous-ready (UPX_RDY_L). The glue logic indicates
UPX_DATA[31:0]
UPX_ADD[10:0]
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
UPX_ADD[10:0]
address to be read should be on the IXF1110 MAC address bus (UPX_ADD[10:0]).
The IXF1110 MAC latches the data.
to the CPU that the Write cycle is complete.
UPX_RDY_L
UPX_RDY_L
UPX_CS_L
UPX_RD_L
UPX_WR_L
UPX_CS_L
provides the timing of the asynchronous interface for Write access.
T
CAS
Tcas
Tcdrh
T
Tcdrs
CWL
T
CDWS
Tcrr
T
CDWD
T
CAH
Tcdrh
Tcah
Tcrh
T
CDWH
T
CYD
5.6 CPU Interface
T
CWH
B3381-01
B3382-01
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