HFIXF1110CC.B3-998844 Cortina Systems Inc, HFIXF1110CC.B3-998844 Datasheet - Page 47

• Manufacturer Part Number: HFIXF1110CC.B3-998844
• Description: IC ETHERNET MAC 10PORT 552-CBGA
• Manufacturer: Cortina Systems Inc

Specifications of HFIXF1110CC.B3-998844

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-4.2
• Voltage - Supply: 1.8 V, 2.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1010

IXF1110 MAC
Datasheet
250210, Revision 11.0
13 April 2009
5.1.3.1.4
Note:
Note:
Table 15
Cortina Systems
The IXF1110 MAC response to valid received PAUSE frames is independent of the PAUSE
frame filter settings. Refer to
additional details.
Transmit Pause Control Interface
The Transmit Pause Control interface allows an external device to trigger the generation of
pause frames. The Transmit Pause Control interface is completely asynchronous. It
consists of four address signals (TXPAUSEADD[3:0]) and a strobe signal (TXPAUSEFR).
The required address for this interface operation is placed on the TXPAUSEADD[3:0]
signals and the TXPAUSEFR is pulsed High and returned Low. Refer to
Pause Control Interface, on page 48
page
decodes for the TXPAUSEADD[3:0] signals.
page 48
Flow control must be enabled in the
Transmit Pause Control interface operation.
There are two additional decodes provided that allow the user to generate either an XOFF
frame or XON frame from all ports simultaneously.
The default pause quanta for each port is held by the
0x07), on page
Valid Decodes for TXPAUSEADD[3:0] (Sheet 1 of 2)
®
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
1. The IXF1110 MAC checks the entire frame to verify that it is a valid PAUSE control
2. If the PAUSE frame is valid, the transmit side of the IXF1110 MAC pauses for the
3. PAUSE does not begin until completion of the frame currently being transmitted.
TXPAUSEADD[3:0]
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
frame addressed to the Multicast Address 01-80-C2-00-00-01 (as specified in IEEE
802.3, Annex 31B) or has a Destinations Address matching the address programmed in
the
High ($ Port_Index + 0x01), on page
required number of PAUSE Quanta, as specified in IEEE 802.3, Clause 31.
108.
Station Address Low ($ Port_Index + 0x00), on page 125
illustrates the transmit pause control interface.
Table 15, Valid Decodes for TXPAUSEADD[3:0], on page 47
125). The default value of this register is 0x05E after reset is applied.
Transmits a PAUSE frame on every port with a pause_time = ZERO (XON)
(Cancels all previous pause commands).
Transmits a PAUSE frame on port 0 with pause_time equal to the value programmed
in the port 0
Transmits a PAUSE frame on port 1 with pause_time equal to the value programmed
in the port 1
Transmits a PAUSE frame on port 2 with pause_time equal to the value programmed
in the port 2
Transmits a PAUSE frame on port 3 with pause_time equal to the value programmed
in the port 3
Transmits a PAUSE frame on port 4 with pause_time equal to the value programmed
in the port 4
Transmits a PAUSE frame on port 5 with pause_time equal to the value programmed
in the port 5
Transmits a PAUSE frame on port 6 with pause_time equal to the value programmed
in the port 6
Section 5.1.2.3.5, Filter PAUSE Packets, on page 43
FC TX Timer Value ($ Port_Index + 0x07)
FC TX Timer Value ($ Port_Index + 0x07)
FC TX Timer Value ($ Port_Index + 0x07)
FC TX Timer Value ($ Port_Index + 0x07)
FC TX Timer Value ($ Port_Index + 0x07)
FC TX Timer Value ($ Port_Index + 0x07)
FC TX Timer Value ($ Port_Index + 0x07)
FC Enable ($ Port_Index + 0x12), on page 127
and
TX Pause Control Interface Operation
125.
Transmit Pause Control Interface Parameters, on
Figure 8, Transmit Pause Control Interface, on
FC TX Timer Value ($ Port_Index +
(XOFF).
(XOFF).
(XOFF).
(XOFF).
(XOFF).
(XOFF).
(XOFF).
5.1 Media Access Controller
through
shows the valid
Figure 8, Transmit
Station Address
for
for
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