HFIXF1110CC.B3-998844 Cortina Systems Inc, HFIXF1110CC.B3-998844 Datasheet - Page 88

• Manufacturer Part Number: HFIXF1110CC.B3-998844
• Description: IC ETHERNET MAC 10PORT 552-CBGA
• Manufacturer: Cortina Systems Inc

Specifications of HFIXF1110CC.B3-998844

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-4.2
• Voltage - Supply: 1.8 V, 2.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1010

IXF1110 MAC
Datasheet
250210, Revision 11.0
13 April 2009
5.6.2.3
5.6.3
5.7
5.7.1
Note:
Table 29
Cortina Systems
Timing parameters
Timing parameters for the CPU interface are seen in
page
Endian
The Endian of the CPU interface may be changed to allow connection of various CPUs to
the IXF1110 MAC. The Endian selection is determined by setting the Endian bit in the
Interface ($ 0x508), on page
JTAG (Boundary Scan)
The IXF1110 MAC includes an IEEE 1149.1 boundary scan test port for board level testing.
All inputs are accessible. The BSDL file for this device is available by accessing the Cortina
website.
TAP Interface (JTAG)
The IXF1110 MAC includes an IEEE 1149.1 compliant Test Access Port (TAP) interface
used during boundary scan testing. The interface consists of the following five pins:
TDI and TMS require external pull-up resistors to float the pins High per the IEEE 1149.1
specification. Pull-ups are recommended on TCK and TDO. For normal operation, TRST_L
can be pulled Low, permanently disabling the JTAG interface. If the JTAG interface is used,
the TAP controller must be reset as described in
page 89
The JTAG pins must be terminated correctly for proper device operation.
Recommended JTAG Termination
®
Signal
TRST_L1
TDO
TDI
TMS
TCK
1. TRST_L must be pulled Low to ensure proper IXF1110 MAC operation. When TRST_L is Low, the JTAG
• TDI – Serial data input
• TMS – Test mode select
• TCLK – TAP clock
• TRST_L – Active low asynchronous reset for the TAP
• TDO – Serial data output
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
interface is disabled. If the boundary scan logic is used, TRST_L must be pulsed Low after power-up to
ensure reset of the TAP controller. For more information, refer to
page 89
106.
and returned to a logic High.
or the IEEE 1149.1 Boundary Scan Specification.
Description
Pull-down through 10 K Ω resistor
Pull-up through 10 K Ω resistor
Pull-up through 10 K Ω resistor
Pull-up through 10 K Ω resistor
Pull-up through 10 K Ω resistor
142.
Section 5.7.2, TAP State Machine, on
Table 39, CPU Timing Parameters, on
Section 5.7.2, TAP State Machine , on
5.7 JTAG (Boundary Scan)
Page 88
CPU