HFIXF1110CC.B3-998844 Cortina Systems Inc, HFIXF1110CC.B3-998844 Datasheet - Page 53

• Manufacturer Part Number: HFIXF1110CC.B3-998844
• Description: IC ETHERNET MAC 10PORT 552-CBGA
• Manufacturer: Cortina Systems Inc

Specifications of HFIXF1110CC.B3-998844

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-4.2
• Voltage - Supply: 1.8 V, 2.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1010

IXF1110 MAC
Datasheet
250210, Revision 11.0
13 April 2009
5.1.8.3
Note:
5.2
Cortina Systems
Additional Statistics
The following additional IXF1110 MAC registers support features not documented in RMON:
These additional counters allow for additional differentiation over and above standard
RMON probes.
A packet transfer with an invalid 10-bit symbol will not always update the statistics registers
correctly.
System Packet Interface Level 4 Phase 2
The System Packet Interface Level 4 Phase 2 (SPI4-2) provides a high-speed connection to
a network processor or an ASIC. The interface implemented on the IXF1110 MAC operates
at data rates up to 12.8 Gbps and supports up to ten 1 Gbps MAC ports. The data path is
16 lanes wide in each direction, with each lane operating from 640 Mbps up to 800 Mbps.
Port addressing, start/end packet control, and error control codes are all transferred
“in-band” on the data bus. In-band addressing supports up to 10 ports. Separate transmit
and receive FIFO status lines are used for flow control. By keeping the FIFO status
®
• Good Packets: Error-free packets that have a valid frame length. For example, on
• Bad Packets: Packets that have proper framing and are therefore recognized as
• MAC (flow) control frames
• VLAN tagged frames
• Sequence errors
• Symbol errors
• CRC errors
• Behavior: The IXF1110 MAC 8B10B decoder substitutes a valid code word octet in its
• Issue: If the invalid 10-bit code is inserted in a byte position of 64 or greater, expected
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
Ethernet, good packets are error-free packets that are between 64 octets long and 1518
octets long. They follow the form defined in IEEE 802.3, Section 3.2.
packets, but contain errors within the packet or have an invalid length. For example, on
Ethernet, bad packets have a valid preamble and SFD, but have a bad CRC, or are
either shorter than 64 octets or longer than 1518 octets.
place. The packet transfer is aborted and marked as bad. The new internal length of the
packet is equal to the byte position where the invalid symbol was. No packet fragments
are seen at the next packet transfer.
RX statistics are reported. However, if the invalid code is inserted in a byte position of
less than 64, expected RX statistics are not stored.
5.2 System Packet Interface Level 4
Page 53
Phase 2