HFIXF1110CC.B3-998844 Cortina Systems Inc, HFIXF1110CC.B3-998844 Datasheet - Page 86

• Manufacturer Part Number: HFIXF1110CC.B3-998844
• Description: IC ETHERNET MAC 10PORT 552-CBGA
• Manufacturer: Cortina Systems Inc

Specifications of HFIXF1110CC.B3-998844

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-4.2
• Voltage - Supply: 1.8 V, 2.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1010

IXF1110 MAC
Datasheet
250210, Revision 11.0
13 April 2009
Note:
5.6.2.1
Cortina Systems
UPX_CS_L
The chip select input when active Low selects IXF1110 MAC for the current cycle. No CPU
cycle is recognized without this signal being active. At the end of the cycle, the chip select
can be driven High to deselect the device or it can be left active if the next access is to the
same device (as long as both Read and Write control signals are inactive between cycles).
The CPU usually supports multiple chip selects, and glue logic is required to drive separate
chip selects if more than one IXF1110 MAC is being controlled by one CPU.
UPX_DATA[31:0]
These pins comprise the 32-bit data bus pins containing data to and from the CPU interface.
This data is asynchronous on the IXF1110 MAC. The Write data provided by the CPU must
be stable during the entire CPU cycle to prevent erroneous Write operations to a register.
UPX_WR_L
This pin indicates there is data on the CPU data bus to be written to the IXF1110 MAC. A
Low-to-High transition latches the data and a High-to-Low transition latches the address.
This Write operation is active Low.
UPX_RD_L
This pin indicates there is data on the CPU data bus to be read from the IXF1110 MAC. A
High-to-Low transition latches the address. This Read operation is active Low.
UPX_RDY_L
This pin indicates the Read or Write cycle is complete for the IXF1110 MAC. This operation
is active Low.
External pull-up resistor required for proper operation.
Read Access
The IXF1110 MAC read access cycle operation is done in the following order:
Figure 26
®
1. Chip Select (UPX_CS_L) is asserted at all times for the duration of the operation. The
2. UPX_RD_L should be asserted by the CPU. The IXF1110 MAC latches the address.
3. IXF1110 MAC drives valid data onto the processor bus (UPX_DATA[31:0]).
4. IXF1110 MAC asserts asynchronous-ready (UPX_RDY_L). This indicates to the CPU
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
address to be read should be on the IXF1110 MAC address bus (UPX_ADD[10:0]).
that the Read cycle is complete.
provides the timing of the asynchronous interface for Read access.
5.6 CPU Interface
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