HFIXF1110CC.B3-998844 Cortina Systems Inc, HFIXF1110CC.B3-998844 Datasheet - Page 89

• Manufacturer Part Number: HFIXF1110CC.B3-998844
• Description: IC ETHERNET MAC 10PORT 552-CBGA
• Manufacturer: Cortina Systems Inc

Specifications of HFIXF1110CC.B3-998844

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-4.2
• Voltage - Supply: 1.8 V, 2.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1010

IXF1110 MAC
Datasheet
250210, Revision 11.0
13 April 2009
5.7.2
5.7.3
Table 30
5.7.4
Note:
5.7.5
5.7.6
Cortina Systems
TAP State Machine
The TAP pins drive a TAP controller, which implements the 16-state machine specified by
the IEEE 1149.1 specification. Following power up, the TAP controller must be reset by one
of following two mechanisms:
This ensures that the boundary scan cells do not block the pin to core connections in
theIXF1110 MAC.
Instruction Register and Supported Instructions
The instruction register is a 4-bit register that enacts the boundary scan instructions. After
the state machine resets, the default instruction is IDCODE. The decode logic in the TAP
controller selects the appropriate data register and configures the boundary scan cells for
the current instruction. The table below shows the supported boundary scan instructions.
Supported Boundary Scan Instructions
ID Register
The ID register is a 32-bit register. The IDCODE instruction connects this register between
TDI and TDO. Refer to
descriptions.
The four bit version field is stepping dependent. The seven bit Manufacturers ID is the
manufacturer JEDEC ID less the parity bit per the IEEE 1149.1 specification.
Boundary Scan Register
The boundary scan register is a shift register made up of all the boundary scan cells
associated with the device pins. The number, type, and order of the boundary scan cells are
specified in the IXF1110 MAC BSDL file. The EXTEST and SAMPLE instructions connect
this register between TDI and TDO.
Bypass Register
The bypass register is a one bit register that is used so the IXF1110 MAC can be bypassed
to reduce the length of the JTAG chain when trying to access other devices on the chain
besides the IXF1110 MAC. The BYPASS, HIGHZ, and CLAMP instructions connect this
register between TDI and TDO.
®
• Asynchronous reset – achieved by pulsing or holding TRST_L low
• Synchronous reset – achieved by clocking TCK with five clock pulses while TMS is held
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
Instruction
or floats High.
SAMPLE
EXTEST
IDCODE
BYPASS
CLAMP
HIGHZ
Code
0000
0001
0101
0110
0111
1111
Table 87, JTAG ID Revision ($ 0x50C), on page 144
ID Code Inspection
Sample Boundary
Clamp Boundary
Float Boundary
External Test
Description
1-bit Bypass
Boundary Scan
Boundary Scan
Data Register
5.7 JTAG (Boundary Scan)
Bypass
Bypass
Bypass
ID
for register bit
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