HFIXF1110CC.B3-998844 Cortina Systems Inc, HFIXF1110CC.B3-998844 Datasheet - Page 163

• Manufacturer Part Number: HFIXF1110CC.B3-998844
• Description: IC ETHERNET MAC 10PORT 552-CBGA
• Manufacturer: Cortina Systems Inc

Specifications of HFIXF1110CC.B3-998844

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-4.2
• Voltage - Supply: 1.8 V, 2.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1010

IXF1110 MAC
Datasheet
250210, Revision 11.0
13 April 2009
Table 101
Table 102
Cortina Systems
SPI4-2 RX Burst Size ($ 0x700) (Sheet 2 of 2)
SPI4-2 RX Training ($ 0x701)
®
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
Register Description: SPI4-2 RX interface start-up parameters for training sequences
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
2. The value of DATA_MAX_T is the Most Significant 16 bits of a 24-bit counter value. The Least Significant
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
24:16
31:24
23:16
8 bits are always 0x00. This allows for a much larger DAT_MAX_T time-out period and provides a more
than adequate granularity of selection.
15:9
15:0
8:0
Bit
Bit
MaxBurst1
Reserved
MaxBurst2
Reserved
REP_T
DATA_MAX_T
Name
Name
2
Maximum number of 16-byte blocks that the
FIFO in the receive path, external to the
IXF1110 MAC, can accept when the FIFO
Status channel indicates STARVING.
Note:
Reserved
Maximum number of 16-byte blocks that the
FIFO in the receive path, external to the
IXF1110 MAC, can accept when the FIFO
Status channel indicates HUNGRY.
Note:
Reserved
Number of repetitions of the data training
sequence that must be scheduled every
DATA_MAX_T cycles
Maximum interval (in number of cycles)
between scheduling of training sequences on
receive data path interface
An all zero value disables periodic training
sequences.
Do not program these bits below 0x2
(32 byte burst).
Do not program these bits below 0x2
(32 byte burst).
Description
Description
Type
Type
R/W
R/W
R/W
R/W
R
R
1
1
8.5 Memory Map
0x00000000
Default
Default
0x006
0x002
0x0000
0x00
0x00
0x00
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