HFIXF1110CC.B3-998844 Cortina Systems Inc, HFIXF1110CC.B3-998844 Datasheet - Page 54

• Manufacturer Part Number: HFIXF1110CC.B3-998844
• Description: IC ETHERNET MAC 10PORT 552-CBGA
• Manufacturer: Cortina Systems Inc

Specifications of HFIXF1110CC.B3-998844

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-4.2
• Voltage - Supply: 1.8 V, 2.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1010

IXF1110 MAC
Datasheet
250210, Revision 11.0
13 April 2009
Figure 9
Table 17
Cortina Systems
information out-of-band, the transmit and receive interfaces may be de-coupled to operate
independently.
interface.
SPI4-2 Interfacing with the Network Processor or Forwarding Engine
SPI4-2 Interface Signal Summary (Sheet 1 of 2)
®
TDAT[15:0]_P/N
TDCLK_P/N
TCTL_P/N
TSCLK
TSTAT1, TSTAT0
RDAT[15:0]_P/N
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
Signal Name
IXF1x10
MAC
Figure 9
RDAT[15:0]_P/N
TDAT[15:0]_P/N
RDCLK_P/N
TDCLK_P/N
Transmit Data Bus: Differential LVDS lines used to carry payload data and in-band
control words.
Internally terminated differentially with 100 Ω.
Transmit Data Clock: Differential LVDS clock associated with TDAT[15:0] and TCTL.
Data and control lines are driven off the rising and falling edges of the clock.
Internally terminated differentially with 100 Ω.
NOTE: If TDCLK is applied to the IXF1110 MAC after the device has come out of
reset, the system designer must ensure the TDCLK is stable when applied. Failure to
due so can result in the IXF1110 MAC training on a non-stable clock, causing DIP4
errors and data corruption.
Transmit Control: Differential LVDS lines used to indicate when a control word is
being transmitted. A High level indicates a control word present on TDAT[15:0].
Internally terminated differentially with 100 Ω.
Transmit Status Clock: LVTTL clock associated with TSTAT [1:0].
Frequency is equal to one-quarter TDCLK.
Transmit FIFO Status: LVTTL lines used to carry round-robin FIFO status
information, along with associated error detection and framing.
Receive Data: Carries payload data and in-band control from the IXF1110 MAC
link-layer device.
Internally terminated differentially with 100 Ω
RSTAT[1:0]
TSTAT[1:0]
RCTL_P/N
TCTL_P/N
RSCLK
TSCLK
and
Table 17
Receive
Control
Transmit
provide an overview of the IXF1110 MAC SPI4-2
Control
Data
Data
Signals
SPI-4.2
Transmit
Receive
FIFO Status/
Flow Control
FIFO Status/
Flow Control
Signal Description
Transmit
Receive
5.2 System Packet Interface Level 4
TSCLK
TSTAT[1:0]
TDCLK_P/N
TDAT[15:0]_P/N
TCTL_P/N
RSCLK
RSTAT[1:0]
RDCLK_P/N
RDAT[15:0]_P/N
RCTL_P/N
or Forwarding Engine
with SPI4-2 Interface
Network Processor
B3432-01
Page 54
Phase 2