HFIXF1110CC.B3-998844 Cortina Systems Inc, HFIXF1110CC.B3-998844 Datasheet - Page 94

• Manufacturer Part Number: HFIXF1110CC.B3-998844
• Description: IC ETHERNET MAC 10PORT 552-CBGA
• Manufacturer: Cortina Systems Inc

Specifications of HFIXF1110CC.B3-998844

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-4.2
• Voltage - Supply: 1.8 V, 2.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1010

IXF1110 MAC
Datasheet
250210, Revision 11.0
13 April 2009
Figure 30
6.3.1
Note:
6.3.1.1
Cortina Systems
Packet Buffering FIFO
TX FIFO
The IXF1110 MAC TX FIFOs are implemented with 4.5 KB for each port. This provides
enough space for at least one maximum size packet per-port storage and ensures that no
under-run conditions occur, assuming that the sending device can supply data at the
required data rate.
The TX FIFO High and Low Watermark must be programmed correctly to ensure that the
TX FIFO does not overflow.
MAC Transfer Threshold
The
parameter, which is user programmable, determines when data is transmitted out of the TX
FIFO to the MAC. This parameter is configurable for specific block sizes and the user must
ensure that an under-run does not occur. The threshold must be set to a value that exceeds
the programmed MaxBurst1 parameter from the Network Processor (NPU) or SPI4-2 ASIC.
This method of operation eliminates the possibility of under-run, except when the controlling
NPU device fails.
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
Note:
TX FIFO MAC Transfer Threshold Ports 0 to 9 ($ 0x614 - 0x61D), on page 157
SPI4-2 Interface
High Water Mark
MAC Transfer
Threshold *
Low Water Mark
High Water Mark
Low Water Mark
TxPauseFr (External
The MAC Transfer Threshold determines when the transmit data is transferred from the TX
FIFO to the TX side of the MAC. Once the data has been sent from the TX FIFO to the MAC, it
will be transmitted to the PHY and cannot be flow controlled from the link partner.
strobe)
TX FIFO
RX FIFO
802.3 Flow
control
RX FIFO High
Data Flow
Data Flow
802.3x Pause Frame Generation
6.3 TX FIFO and RX FIFO Operation
TX Side
MAC
RX Side
MAC
MDI
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