HFIXF1110CC.B3-998844 Cortina Systems Inc, HFIXF1110CC.B3-998844 Datasheet - Page 165

• Manufacturer Part Number: HFIXF1110CC.B3-998844
• Description: IC ETHERNET MAC 10PORT 552-CBGA
• Manufacturer: Cortina Systems Inc

Specifications of HFIXF1110CC.B3-998844

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-4.2
• Voltage - Supply: 1.8 V, 2.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1010

IXF1110 MAC
Datasheet
250210, Revision 11.0
13 April 2009
Table 104
8.5.8
Table 105
Cortina Systems
SPI4-2 TX Synchronization ($ 0x703)
SerDes Register Overview
Table 105
at base location 0x780 which contain the control and status for the ten SerDes interfaces on
the IXF1110 MAC.
SerDes Tx Driver Power Level Ports 0-6 ($ 0x784)
®
Register Description: SPI4-2 synchronization DIP-4 counters.
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
2. When Periodic Training is enabled, the actual count of DIP4 errors required to lose synchronization is 1
Register Description: Allows selection of various programmable drive strengths on each of
the SerDes ports.
Note:
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
31:16
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
31:28
27:25
24:21
20:16
15:12
15:8
11:8
Bit
7:0
Bit
7:4
3:0
less than the programmed value in this register. Therefore, this value should always be programmed to be
1 more than the desired value and should never be programmed to either 0 or 1.
Refer to
power levels.
DIP4_Errors
DIP4_UnLock
DIP4_Lock
through
Reserved
DRVPWR6[3:0] Encoded input that sets Power Level for Port 6
DRVPWR5[3:0] Encoded input that sets Power Level for Port 5
DRVPWR4[3:0] Encoded input that sets Power Level for Port 4
DRVPWR3[3:0] Encoded input that sets Power Level for Port 3
DRVPWR2[3:0] Encoded input that sets Power Level for Port 2
DRVPWR1[3:0] Encoded input that sets Power Level for Port 1
DRVPWR0[3:0] Encoded input that sets Power Level for Port 0
Name
Table 21, SerDes Driver TX Power Levels , on page 69
Name
Table 107 on page 166
2
Reserved
DIP4_Errors is the total number of DIP4
errors detected since this register was last
read.
DIP-4_Unlock is a SPI4-2 parameter
specifying the number of incorrect DIP4
fields to be detected to declare loss of
synchronization and drive the TSTAT[1:0]
bus with framing.
Number of consecutive correct DIP4 results
to achieve synchronization and end training
Description
Description
define the contents of the SerDes Register Block
for valid SerDes
Type
CoR
R/W
R/W
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
1
1
8.5 Memory Map
0X00000000
0x00000420
Default
Default
0x0000
1101
1101
1101
1101
1101
1101
1101
0x04
0x20
0x0
Page 165