S9S12HZ128J3VAL Freescale Semiconductor, S9S12HZ128J3VAL Datasheet - Page 123

• Manufacturer Part Number: S9S12HZ128J3VAL
• Description: IC MCU FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HZ128J3VAL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, I²C, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 112-LQFP
• Processor Series: S12HY
• Core: HCS12X
• Data Bus Width: 16 bit
• Data Ram Size: 6 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 1
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.3
This section provides a detailed description of all registers.
integration module.
Freescale Semiconductor
0x001F - 0x002F
0x0006 - 0x0007
Address Offset
Memory Map and Register Definition
0x000C
0x000D
0x001C
0x001D
0x000A
0x000B
0x000E
0x000F
0x001A
0x001B
0x001E
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
0x0008
0x0009
0x0010
0x0011
0x0012
0x0013
0x0014
0x0015
0x0016
0x0017
0x0018
0x0019
Port T I/O Register (PTT)
Port T Input Register (PTIT)
Port T Data Direction Register (DDRT)
Port T Reduced Drive Register (RDRT)
Port T Pull Device Enable Register (PERT)
Port T Polarity Select Register (PPST)
Reserved
Port S I/O Register (PTS)
Port S Input Register (PTIS)
Port S Data Direction Register (DDRS)
Port S Reduced Drive Register (RDRS)
Port S Pull Device Enable Register (PERS)
Port S Polarity Select Register (PPSS)
Port S Wired-OR Mode Register (WOMS)
Reserved
Port M I/O Register (PTM)
Port M Input Register (PTIM)
Port M Data Direction Register (DDRM)
Port M Reduced Drive Register (RDRM)
Port M Pull Device Enable Register (PERM)
Port M Polarity Select Register (PPSM)
Port M Wired-OR Mode Register (WOMM)
Reserved
Port P I/O Register (PTP)
Port P Input Register (PTIP)
Port P Data Direction Register (DDRP)
Port P Reduced Drive Register (RDRP)
Port P Pull Device Enable Register (PERP)
Port P Polarity Select Register (PPSP)
Port P Wired-OR Mode Register (WOMP)
Reserved
Table 4-2. PIM9HZ256 Memory Map
MC9S12HZ256 Data Sheet, Rev. 2.05
Use
Table 4-2
Chapter 4 Port Integration Module (PIM9HZ256V2)
is a standard memory map of port
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
—
—
—
R
R
R
R
123