S9S12HZ128J3VAL Freescale Semiconductor, S9S12HZ128J3VAL Datasheet - Page 131

• Manufacturer Part Number: S9S12HZ128J3VAL
• Description: IC MCU FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HZ128J3VAL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, I²C, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 112-LQFP
• Processor Series: S12HY
• Core: HCS12X
• Data Bus Width: 16 bit
• Data Ram Size: 6 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 1
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.3.2.2
Read: Anytime. Write: Never, writes to this register have no effect.
If the LCD frontplane driver of an associated I/O pin is enabled (and LCD module is enabled) or the
associated ATDDIEN0 bit is set to 0 (digital input buffer is disabled), a read returns a 1.
If the LCD frontplane driver of an associated I/O pin is disabled (or LCD module is disabled) and the
associated ATDDIEN0 bit is set to 1 (digital input buffer is enabled), a read returns the status of the
associated pin.
4.3.2.3
Read: Anytime. Write: Anytime.
This register configures port pins PL[7:0] as either input or output.
If a LCD frontplane driver is enabled (and LCD module is enabled), it outputs an analog signal to the
corresponding pin and the associated Data Direction Register bit has no effect. If a LCD frontplane driver
is disabled (or LCD module is disabled), the corresponding Data Direction Register bit reverts to control
the I/O direction of the associated pin.
Freescale Semiconductor
DDRL[7:0]
Reset
Reset
Field
7:0
W
W
R
R
DDRL7
PTIL7
Data Direction Port L
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Port L Input Register (PTIL)
Port L Data Direction Register (DDRL)
1
0
7
7
= Reserved or Unimplemented
DDRL6
PTIL6
1
0
6
6
Figure 4-12. Port L Data Direction Register (DDRL)
Figure 4-11. Port L Input Register (PTIL)
Table 4-9. DDRL Field Descriptions
DDRL5
PTIL5
MC9S12HZ256 Data Sheet, Rev. 2.05
1
0
5
5
DDRL4
PTIL4
1
0
4
4
Description
DDRL3
PTIL3
1
0
3
3
Chapter 4 Port Integration Module (PIM9HZ256V2)
DDRL2
PTIL2
1
0
2
2
DDRL1
PTIL1
1
0
1
1
DDRL0
PTIL0
1
0
0
0
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