S9S12HZ128J3VAL Freescale Semiconductor, S9S12HZ128J3VAL Datasheet - Page 458

• Manufacturer Part Number: S9S12HZ128J3VAL
• Description: IC MCU FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HZ128J3VAL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, I²C, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 112-LQFP
• Processor Series: S12HY
• Core: HCS12X
• Data Bus Width: 16 bit
• Data Ram Size: 6 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 1
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 15 Pulse-Width Modulator (PWM8B6CV1)
Read: anytime
Write: anytime (any value written causes PWM counter to be reset to 0x0000).
15.3.2.13 PWM Channel Period Registers (PWMPERx)
There is a dedicated period register for each channel. The value in this register determines the period of
the associated PWM channel.
The period registers for each channel are double buffered so that if they change while the channel is
enabled, the change will NOT take effect until one of the following occurs:
In this way, the output of the PWM will always be either the old waveform or the new waveform, not some
variation in between. If the channel is not enabled, then writes to the period register will go directly to the
latches as well as the buffer.
Reference
458
Reset
Reset
Reset
•
•
•
W
W
W
R
R
R
The effective period ends
The counter is written (counter resets to 0x0000)
The channel is disabled
Section 15.4.2.3, “PWM Period and Duty,”
Bit 7
Bit 7
Bit 7
0
0
0
0
0
0
7
7
7
Reads of this register return the most recent value written. Reads do not
necessarily return the value of the currently active period due to the double
buffering scheme.
Figure 15-18. PWM Channel Counter Registers (PWMCNT3)
Figure 15-19. PWM Channel Counter Registers (PWMCNT4)
Figure 15-20. PWM Channel Counter Registers (PWMCNT5)
6
0
0
6
0
0
6
0
0
6
6
6
MC9S12HZ256 Data Sheet, Rev. 2.05
5
0
0
5
0
0
5
0
0
5
5
5
NOTE
4
0
0
4
0
0
4
0
0
4
4
4
for more information.
3
0
0
3
0
0
3
0
0
3
3
3
2
0
0
2
0
0
2
0
0
2
2
2
Freescale Semiconductor
1
0
0
1
0
0
1
0
0
1
1
1
Bit 0
Bit 0
Bit 0
0
0
0
0
0
0
0
0
0