S9S12HZ128J3VAL Freescale Semiconductor, S9S12HZ128J3VAL Datasheet - Page 127

• Manufacturer Part Number: S9S12HZ128J3VAL
• Description: IC MCU FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HZ128J3VAL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, I²C, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 112-LQFP
• Processor Series: S12HY
• Core: HCS12X
• Data Bus Width: 16 bit
• Data Ram Size: 6 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 1
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.3.1.4
Read: Anytime. Write: Anytime.
This register configures the drive strength of configured output pins as either full or reduced. If a pin is
configured as input, the corresponding Reduced Drive Register bit has no effect.
4.3.1.5
Read: Anytime. Write: Anytime.
This register configures whether a pull-up or a pull-down device is activated on configured input pins. If
a pin is configured as output, the corresponding Pull Device Enable Register bit has no effect.
Freescale Semiconductor
RDRAD[7:0]
PERAD[7:0]
Reset
Reset
Field
Field
7:0
7:0
W
W
R
R
RDRAD7
PERAD7
Reduced Drive Port AD
0 Full drive strength at output.
1 Associated pin drives at about 1/3 of the full drive strength.
Pull Device Enable Port AD
0 Pull-up or pull-down device is disabled.
1 Pull-up or pull-down device is enabled.
Port AD Reduced Drive Register (RDRAD)
Port AD Pull Device Enable Register (PERAD)
0
0
7
7
RDRAD6
PERAD6
Figure 4-6. Port AD Pull Device Enable Register (PERAD)
0
0
6
6
Figure 4-5. Port AD Reduced Drive Register (RDRAD)
Table 4-4. RDRAD Field Descriptions
Table 4-5. PERAD Field Descriptions
RDRAD5
PERAD5
MC9S12HZ256 Data Sheet, Rev. 2.05
0
0
5
5
RDRAD4
PERAD4
0
0
4
4
Description
Description
RDRAD3
PERAD3
0
0
3
3
Chapter 4 Port Integration Module (PIM9HZ256V2)
RDRAD2
PERAD2
0
0
2
2
RDRAD1
PERAD1
0
0
1
1
RDRAD0
PERAD0
0
0
0
0
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