S9S12HZ128J3VAL Freescale Semiconductor, S9S12HZ128J3VAL Datasheet - Page 268

• Manufacturer Part Number: S9S12HZ128J3VAL
• Description: IC MCU FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HZ128J3VAL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, I²C, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 112-LQFP
• Processor Series: S12HY
• Core: HCS12X
• Data Bus Width: 16 bit
• Data Ram Size: 6 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 1
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 9 Motor Controller (MC10B8CV1)
9.3.2.4
Each PWM channel has one associated control register to control output delay, PWM alignment, and
output mode. The registers are named MCCC0... MCCC7. In the following, MCCC0 is described as a
reference for all eight registers.
268
MCOM[1:0]
MCAM[1:0]
Reset
CD[1:0]
Field
7:6
5:4
1:0
W
R
MCOM1
Output Mode — MCOM1, MCOM0 control the PWM channel’s output mode. See
PWM Channel Delay — Each PWM channel can be individually delayed by a programmable number of PWM
PWM Channel Alignment Mode — MCAM1, MCAM0 control the PWM channel’s PWM alignment mode and
Motor Controller Channel Control Registers
7
0
Figure 9-7. Motor Controller Control Register Channel 0–7 (MCCC0–MCCC7)
operation. See
MCAM[1:0] and MCOM[1:0] are double buffered. The values used for the generation of the output waveform
will be copied to the working registers either at once (if all PWM channels are disabled or MCPER is set to 0)
or if a timer counter overflow occurs. Reads of the register return the most recent written value, which are not
necessarily the currently active values.
timer counter clocks. The delay will be n/f
MCOM[1:0]
MCAM[1:0]
= Unimplemented or Reserved
MCOM0
00
01
10
11
00
01
10
11
6
0
Table
Table 9-5. MCCC0–MCCC7 Field Descriptions
9-7.
Half H-bridge mode, PWM on MnCxM, MnCxP is released
Half H-bridge mode, PWM on MnCxP, MnCxM is released
MCAM1
MC9S12HZ256 Data Sheet, Rev. 2.05
Table 9-7. PWM Alignment Mode
5
0
Table 9-6. Output Mode
MCAM0
Dual full H-bridge mode
PWM Alignment Mode
TC
4
0
Full H-bridge mode
. See
Channel disabled
Center aligned
Output Mode
Right aligned
Description
Left aligned
Table
9-8.
3
0
0
2
0
0
Table
Freescale Semiconductor
CD1
9-6.
1
0
CD0
0
0