S9S12HZ128J3VAL Freescale Semiconductor, S9S12HZ128J3VAL Datasheet - Page 170

• Manufacturer Part Number: S9S12HZ128J3VAL
• Description: IC MCU FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HZ128J3VAL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, I²C, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 112-LQFP
• Processor Series: S12HY
• Core: HCS12X
• Data Bus Width: 16 bit
• Data Ram Size: 6 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 1
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 5 Clocks and Reset Generator (CRGV4)
5.2.3
RESET is an active low bidirectional reset pin. As an input it initializes the MCU asynchronously to a
known start-up state. As an open-drain output it indicates that an system reset (internal to MCU) has been
triggered.
5.3
This section provides a detailed description of all registers accessible in the CRG.
5.3.1
Table 5-1
170
1
2
3
CTFLG is intended for factory test purposes only.
FORBYP is intended for factory test purposes only.
CTCTL is intended for factory test purposes only.
Memory Map and Register Definition
Address
gives an overview on all CRG registers.
0x000A
0x000B
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
0x0006
0x0007
0x0008
0x0009
Offset
RESET — Reset Pin
Module Memory Map
CRG Synthesizer Register (SYNR)
CRG Reference Divider Register (REFDV)
CRG Test Flags Register (CTFLG)
CRG Flags Register (CRGFLG)
CRG Interrupt Enable Register (CRGINT)
CRG Clock Select Register (CLKSEL)
CRG PLL Control Register (PLLCTL)
CRG RTI Control Register (RTICTL)
CRG COP Control Register (COPCTL)
CRG Force and Bypass Test Register (FORBYP)
CRG Test Control Register (CTCTL)
CRG COP Arm/Timer Reset (ARMCOP)
Figure 5-2. PLL Loop Filter Connections
MCU
MC9S12HZ256 Data Sheet, Rev. 2.05
Table 5-1. CRG Memory Map
XFC
1
3
Use
RS
CS
2
CP
V
DDPLL
Freescale Semiconductor
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W