S9S12HZ128J3VAL Freescale Semiconductor, S9S12HZ128J3VAL Datasheet - Page 681

• Manufacturer Part Number: S9S12HZ128J3VAL
• Description: IC MCU FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HZ128J3VAL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, I²C, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 112-LQFP
• Processor Series: S12HY
• Core: HCS12X
• Data Bus Width: 16 bit
• Data Ram Size: 6 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 1
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
0x015C–
0x0150–
0x0154–
0x0158–
0x0160–
0x0170–
0x0164–
0x016C
0x016D
0x014E
0x014F
0x015B
0x015F
0x016F
0x017F
0x016B
0x016E
0x016F
0x0153
0x0157
0x0160
0x0161
0x0162
0x0163
0x0170
Address
Address
0x0140–0x017F CAN0 (Scalable CAN–MSCAN) (continued)
CAN0RDSR0–
CAN0IDMR0–
CAN0IDMR4–
CAN0RXERR
CAN0TXERR
CAN0IDAR0–
CAN0IDAR4–
CAN0RDSR7
CAN0RTSRH
CAN0RTSRL
CAN0IDMR3
CAN0IDMR7
CAN0RIDR0
CAN0RIDR1
CAN0RIDR2
CAN0RIDR3
CAN0IDAR3
CAN0IDAR7
Extended ID
Extended ID
Extended ID
Extended ID
Extended ID
CAN0TIDR0
CAN0RXFG
CAN0RDLR
CAN0TXFG
Standard ID
Standard ID
Standard ID
Standard ID
Standard ID
Reserved
Name
Name
Table 22-22. Detailed MSCAN Foreground Receive and Transmit Buffer Layout
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
R RXERR7
R TXERR7
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
TSR15
TSR7
AM7
AM7
ID28
ID10
ID20
ID14
ID28
ID10
AC7
AC7
DB7
ID2
ID6
7
7
RXERR6
TXERR6
MC9S12HZ256 Data Sheet, Rev. 2.05
TSR14
TSR6
AM6
AM6
ID27
ID19
ID13
ID27
AC6
AC6
DB6
ID9
ID1
ID5
ID9
6
6
FOREGROUND TRANSMIT BUFFER see
FOREGROUND RECEIVE BUFFER see
RXERR5
TXERR5
TSR13
TSR5
ID26
ID18
ID12
ID26
AM5
AM5
AC5
AC5
DB5
ID8
ID0
ID4
ID8
5
5
RXERR4
TXERR4
SRR=1
TSR12
TSR4
ID25
ID11
ID25
AM4
AM4
RTR
AC4
AC4
DB4
ID7
ID3
ID7
4
4
RXERR3
TXERR3
TSR11
IDE=1
IDE=0
DLC3
TSR3
ID24
ID10
ID24
AM3
AM3
DB3
AC3
AC3
ID6
ID2
ID6
3
3
RXERR2
TXERR2
TSR10
Table 22-22
Appendix G Detailed Register Map
DLC2
TSR2
AM2
AM2
Table 22-22
ID23
ID17
ID23
AC2
AC2
DB2
ID5
ID9
ID1
ID5
2
2
RXERR1
TXERR1
DLC1
TSR9
TSR1
AM1
AM1
ID22
ID16
ID22
AC1
AC1
DB1
ID4
ID8
ID0
ID4
1
1
RXERR0
TXERR0
DLC0
TSR8
TSR0
AM0
AM0
ID21
ID15
RTR
ID21
AC0
AC0
DB0
ID3
ID7
ID3
0
0
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