S9S12HZ128J3VAL Freescale Semiconductor, S9S12HZ128J3VAL Datasheet - Page 349

• Manufacturer Part Number: S9S12HZ128J3VAL
• Description: IC MCU FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HZ128J3VAL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, I²C, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 112-LQFP
• Processor Series: S12HY
• Core: HCS12X
• Data Bus Width: 16 bit
• Data Ram Size: 6 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 1
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.3.2.9
The CANTARQ register allows abort request of queued messages as described below.
Read: Anytime
Write: Anytime when not in initialization mode
Freescale Semiconductor
ABTRQ[2:0]
Field
2:0
Reset:
W
R
Abort Request — The CPU sets the ABTRQx bit to request that a scheduled message buffer (TXEx = 0) be
aborted. The MSCAN grants the request if the message has not already started transmission, or if the
transmission is not successful (lost arbitration or error). When a message is aborted, the associated TXE (see
Section 12.3.2.7, “MSCAN Transmitter Flag Register
Section 12.3.2.10, “MSCAN Transmitter Message Abort Acknowledge Register
transmit interrupt occurs if enabled. The CPU cannot reset ABTRQx. ABTRQx is reset whenever the associated
TXE flag is set.
0 No abort request
1 Abort request pending
Figure 12-10. MSCAN Transmitter Message Abort Request Register (CANTARQ)
MSCAN Transmitter Message Abort Request Register (CANTARQ)
The CANTARQ register is held in the reset state when the initialization
mode is active (INITRQ = 1 and INITAK = 1). This register is writable when
not in initialization mode (INITRQ = 0 and INITAK = 0).
0
0
7
= Unimplemented
Table 12-15. CANTARQ Register Field Descriptions
6
0
0
MC9S12HZ256 Data Sheet, Rev. 2.05
0
0
5
NOTE
Chapter 12 Freescale’s Scalable Controller Area Network (MSCANV2)
4
0
0
Description
(CANTFLG)”) and abort acknowledge flags (ABTAK, see
0
0
3
ABTRQ2
2
0
(CANTAAK)”) are set and a
ABTRQ1
0
1
ABTRQ0
0
0
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