S9S12HZ128J3VAL Freescale Semiconductor, S9S12HZ128J3VAL Datasheet - Page 343

• Manufacturer Part Number: S9S12HZ128J3VAL
• Description: IC MCU FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HZ128J3VAL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, I²C, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 112-LQFP
• Processor Series: S12HY
• Core: HCS12X
• Data Bus Width: 16 bit
• Data Ram Size: 6 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 1
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.3.2.4
The CANBTR1 register configures various CAN bus timing parameters of the MSCAN module.
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
1
Freescale Semiconductor
TSEG2[2:0]
TSEG1[3:0]
In this case, PHASE_SEG1 must be at least 2 time quanta (Tq).
SAMP
Field
6:4
3:0
7
Reset:
W
R
Sampling — This bit determines the number of CAN bus samples taken per bit time.
0 One sample per bit.
1 Three samples per bit
If SAMP = 0, the resulting bit value is equal to the value of the single bit positioned at the sample point. If
SAMP = 1, the resulting bit value is determined by using majority rule on the three total samples. For higher bit
rates, it is recommended that only one sample is taken per bit time (SAMP = 0).
Time Segment 2 — Time segments within the bit time fix the number of clock cycles per bit time and the location
of the sample point (see
Table
Time Segment 1 — Time segments within the bit time fix the number of clock cycles per bit time and the location
of the sample point (see
Table
MSCAN Bus Timing Register 1 (CANBTR1)
SAMP
1
0
7
12-9.
12-10.
This setting is not valid. Please refer to
TSEG22
0
0
1
1
:
Figure 12-5. MSCAN Bus Timing Register 1 (CANBTR1)
TSEG22
Table 12-8. CANBTR1 Register Field Descriptions
6
0
1
Figure
Figure
.
TSEG21
Table 12-9. Time Segment 2 Values
MC9S12HZ256 Data Sheet, Rev. 2.05
TSEG21
0
0
1
1
:
12-41). Time segment 2 (TSEG2) values are programmable as shown in
12-41). Time segment 1 (TSEG1) values are programmable as shown in
0
5
TSEG20
TSEG20
Chapter 12 Freescale’s Scalable Controller Area Network (MSCANV2)
Table 12-36
4
0
0
1
0
1
:
Description
TSEG13
for valid settings.
0
3
Time Segment 2
1 Tq clock cycle
2 Tq clock cycles
7 Tq clock cycles
8 Tq clock cycles
TSEG12
:
2
0
1
TSEG11
0
1
TSEG10
0
0
343