S9S12HZ128J3VAL Freescale Semiconductor, S9S12HZ128J3VAL Datasheet - Page 245

• Manufacturer Part Number: S9S12HZ128J3VAL
• Description: IC MCU FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HZ128J3VAL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, I²C, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 112-LQFP
• Processor Series: S12HY
• Core: HCS12X
• Data Bus Width: 16 bit
• Data Ram Size: 6 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 1
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.3.2
This section consists of register descriptions. Each description includes a standard register diagram.
Details of register bit and field function follow the register diagrams, in bit order.
8.3.2.1
Read: anytime
Write: LCDEN anytime. To avoid segment flicker the clock prescaler bits, the bias select bit and the duty
Freescale Semiconductor
DUTY[1:0]
LCLK[2:0]
LCDEN
Reset
Field
BIAS
5:3
1:0
7
2
W
R
select bits must not be changed when the LCD is enabled.
LCDEN
Register Descriptions
LCD32F4B Driver System Enable — The LCDEN bit starts the LCD waveform generator.
0 All frontplane and backplane pins are disabled. In addition, the LCD32F4B system is disabled
1 LCD driver system is enabled. All FP[31:0] pins with FP[31:0]EN set, will output an LCD driver
LCD Clock Prescaler — The LCD clock prescaler bits determine the OSCCLK divider value to produce the LCD
clock frequency. For detailed description of the correlation between LCD clock prescaler bits and the divider
value please refer to
BIAS Voltage Level Select — This bit selects the bias voltage levels during various LCD operating modes, as
shown in
LCD Duty Select — The DUTY1 and DUTY0 bits select the duty (multiplex mode) of the LCD32F4B driver
system, as shown in
LCD Control Register 0 (LCDCR0)
7
0
and all LCD waveform generation clocks are stopped.
waveform The BP[3:0] pins will output an LCD32F4B driver waveform based on the settings of DUTY0
and DUTY1.
Table
= Unimplemented or Reserved
8-8.
6
0
0
Table
Table
Figure 8-2. LCD Control Register 0 (LCDCR0)
Table 8-3. LCDCR0 Field Descriptions
8-7.
8-8.
LCLK2
MC9S12HZ256 Data Sheet, Rev. 2.05
5
0
LCLK1
4
0
Description
LCLK0
3
0
Chapter 8 Liquid Crystal Display (LCD32F4BV1)
BIAS
2
0
DUTY1
1
0
DUTY0
0
0
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