S9S12HZ128J3VAL Freescale Semiconductor, S9S12HZ128J3VAL Datasheet - Page 425

• Manufacturer Part Number: S9S12HZ128J3VAL
• Description: IC MCU FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HZ128J3VAL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, I²C, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 112-LQFP
• Processor Series: S12HY
• Core: HCS12X
• Data Bus Width: 16 bit
• Data Ram Size: 6 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 1
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.3.2.3
Read: anytime
Write: anytime; writes to the reserved bits have no effect
The baud rate divisor equation is as follows:
The baud rate can be calculated with the following equation:
Freescale Semiconductor
SPPR[2:0]
SPR[2:0}
Reset
Field
6:4
2:0
W
R
SPI Baud Rate Preselection Bits — These bits specify the SPI baud rates as shown in
mode, a change of these bits will abort a transmission in progress and force the SPI system into idle state.
SPI Baud Rate Selection Bits — These bits specify the SPI baud rates as shown in
a change of these bits will abort a transmission in progress and force the SPI system into idle state.
SPI Baud Rate Register (SPIBR)
0
0
7
= Unimplemented or Reserved
SPPR2
0
6
Figure 14-5. SPI Baud Rate Register (SPIBR)
BaudRateDivisor
Table 14-6. SPIBR Field Descriptions
Baud Rate
SPPR1
MC9S12HZ256 Data Sheet, Rev. 2.05
0
5
=
BusClock BaudRateDivisor
SPPR0
=
0
4
SPPR
Description
+
1
0
0
3
2
SPR
Chapter 14 Serial Peripheral Interface (SPIV3)
+
1
SPR2
0
2
Table
SPR1
Table
14-7. In master mode,
0
1
14-7. In master
SPR0
0
0
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