S9S12HZ128J3VAL Freescale Semiconductor, S9S12HZ128J3VAL Datasheet - Page 683

• Manufacturer Part Number: S9S12HZ128J3VAL
• Description: IC MCU FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HZ128J3VAL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, I²C, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 112-LQFP
• Processor Series: S12HY
• Core: HCS12X
• Data Bus Width: 16 bit
• Data Ram Size: 6 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 1
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
0x018C–
0x019C–
0x01A4
0x0190–
0x0194–
0x0198–
0x01A0–
0x01B0–
0x01AD
0x018D
0x01AF
0x01BF
0x01AB
0x01AC
0x01AE
0x018A
0x018B
0x018E
0x018F
0x019B
0x019F
0x01A0
0x01A1
0x01A2
0x01A3
0x0193
0x0197
Address
Address
0x0180–0x01BF CAN1 (Freescale’s Scalable CAN–MSCAN) (continued)
–
Table 22-23. Detailed MSCAN Foreground Receive and Transmit Buffer Layout (Sheet 1 of 2)
CAN1RDSR0–
CAN1IDMR0–
CAN1IDMR4–
CAN1RXERR
CAN1TXERR
CAN1IDAR0–
CAN1IDAR4–
CAN1RDSR7
CAN1RTSRH
CAN1TBSEL
CAN1IDMR3
CAN1IDMR7
CAN1RIDR0
CAN1RIDR1
CAN1RIDR2
CAN1RIDR3
CAN1IDAR3
CAN1IDAR7
Extended ID
Extended ID
Extended ID
Extended ID
CAN1RXFG
CAN1RDLR
CAN1TXFG
Standard ID
Standard ID
Standard ID
Standard ID
CAN1IDAC
Reserved
Reserved
Name
Name
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
R
R
R
R RXERR7
R TXERR7
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
TSR15
AM7
AM7
ID28
ID10
ID20
ID14
AC7
AC7
DB7
ID2
ID6
7
0
0
0
7
RXERR6
TXERR6
MC9S12HZ256 Data Sheet, Rev. 2.05
TSR14
AM6
AM6
ID27
ID19
ID13
AC6
AC6
DB6
ID9
ID1
ID5
0
0
0
6
6
FOREGROUND TRANSMIT BUFFER see
FOREGROUND RECEIVE BUFFER see
RXERR5
TXERR5
TSR13
IDAM1
ID26
ID18
ID12
AM5
AM5
AC5
AC5
DB5
ID8
ID0
ID4
0
0
5
5
RXERR4
TXERR4
SRR=1
IDAM0
TSR12
ID25
ID11
AM4
AM4
RTR
AC4
AC4
DB4
ID7
ID3
0
0
4
4
RXERR3
TXERR3
TSR11
IDE=1
IDE=0
DLC3
ID24
ID10
AM3
AM3
DB3
AC3
AC3
ID6
ID2
0
0
0
3
3
RXERR2
TXERR2
IDHIT2
TSR10
Table 22-22
Appendix G Detailed Register Map
DLC2
AM2
AM2
Table 22-22
ID23
ID17
AC2
AC2
DB2
TX2
ID5
ID9
ID1
0
2
2
RXERR1
TXERR1
IDHIT1
DLC1
TSR9
AM1
AM1
ID22
ID16
AC1
AC1
DB1
TX1
ID4
ID8
ID0
1
0
1
RXERR0
TXERR0
IDHIT0
DLC0
TSR8
AM0
AM0
ID21
ID15
RTR
AC0
AC0
DB0
TX0
ID3
ID7
0
0
0
683