MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 100

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Overview
1.2
This section provides a high-level overview of MPC8533E features.
units within the MPC8533E.
1.2.1
The following list provides an overview of the MPC8533E feature set:
1-2
SDRAM
GMII, RGMII,
GMII, RGMI,
•
GPIO
Flash
IRQs
DDR
TBI, RTBI,
TBI, RTBI,
Serial
MII, RMII
MII, RMII
High-performance 32-bit e500 core that implements resources for embedded processors defined by
the Power ISA:
— 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection. Caches can
— Signal-processing engine (SPE) instructions. Extensive instruction set for vector (64-bit)
— Double-precision (64-bit) floating-point instructions that use the 64-bit GPRs.
— Embedded vector and scalar single-precision (32-bit) floating-point instructions.
— 36-bit real addressing (up to 64 Gbytes of memory)
— Memory management unit (MMU) especially designed for embedded applications that support
I
I
2
2
C
C
MPC8533E Overview
be locked entirely or on a per-line basis, with separate locking for instructions and data.
integer and fractional operations. These instructions use both the upper and lower words of the
64-bit general-purpose registers (GPR) as they are defined by the SPE category of the Power
ISA.
4-Kbyte–4-Gbyte page sizes.
Key Features
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Programmable Interrupt
Local Bus Controller
Memory Controller
Controller (PIC)
DDR/DDR2/
Controller
Controller
10/100/1Gb
10/100/1Gb
DUART
eTSEC
eTSEC
I
I
2
2
C
C
Figure 1-1. MPC8533E Block Diagram
Coherency
OceaN
Switch
Fabric
Security
Module
Engine
Engine
e500
XOR
Core Complex
L2 Cache/
256-Kbyte
32-bit PCI Bus Interface
SRAM
Bus
4-Channel DMA
PCI Express
Controller
Figure 1-1
Interfaces
32-Kbyte L1
Instruction
Cache
shows the major functional
e500 Core
Freescale Semiconductor
32-Kbyte
L1 Data
Cache
PCI 32-bit
66 MHz
dual x4 and
single x1
External
Control