MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 1091

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

cross a 4-byte boundary. The bus number, device number, function number, register, and extended register
number sent are decoded from the outbound translated PCI Express address.
A Type 0 configuration cycle is sent to the link if the bus number equals the secondary bus number (from
the type 1 header) and device number is 0. A Type 1 configuration cycle is sent to the link if bus number
does not equal primary bus and secondary bus numbers and it is less than or equal to the subordinate bus
number (from the type 1 header). For all other cases, the PCI Express controller squashes the write and
read will result in a response with error returned.
Note that the PCI Express controller does not support access to its internal configuration registers using
the outbound ATMU mechanism. That is, the outbound ATMU mechanism must not be used to program
the internal registers.
18.3.7.2
When the PCI Express controller is configured as an EP device it responds to remote host generated
configuration cycles. This is indicated by decoding the configuration command along with type 0 access
in the packet. A remote host can access up to 4096 bytes of the PCI Express configuration area. While in
EP mode, the PCI Express controller does not support generating configuration accesses as a master. All
accesses to PEX_CONFIG_ADDR/PEX_CONFIG_DATA cause the device to access the internal
configuration registers regardless of the bus number or device number programmed in the
PEX_CONFIG_ADDR register. There is no configuration mechanism supported in EP mode using the
ATMU window. If the outbound ATMU window is configured to issue a configuration transaction, all
posted transactions hitting this window are ignored and all non-posted transactions will get a response with
an error.
18.3.8
The first 64 bytes of the 256-byte PCI compatible configuration space consists of a predefined header that
every PCI device must support. The first 16 bytes of the predefined header are defined the same for all PCI
Express devices. These common registers are shown in
Freescale Semiconductor
Reserved
•
•
•
•
•
bus number[7:0] = PCI Express address[27:20]
device number[4:0] = PCI Express address[19:15]
function number[2:0] = PCI Express address[14:12]
extended register number[3:0] = PCI Express address[11:8]
register number[5:0] = PCI Express address[7:2]
Figure 18-36. PCI Express PCI-Compatible Configuration Header Common Registers
PCI Compatible Configuration Headers
BIST
EP Configuration Register Access
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Device ID
Status
Header Type
Class Code
Figure
Latency Timer
18-36.
Command
Vendor ID
PCI Express Interface Controller
Cache Line Size
Revision ID
Offset (Hex)
Address
00
04
08
0C
18-43